BU64240GWZ Datasheet, PDF (4/6 Pages) Rohm – Silicon Monolithic Integrated Circuit

Characteristics of the SDA and SCL bus lines for 2-wire serial interface.
(Unless otherwise specified, Ta=-25～+85°C, VCC=2.3～4.8V )
Parameter
Symbol
STANDARD-MODE^※6
Min.
Max.
LOW level input voltage
VIL
-0.5
0.5
High level input voltage
VIH
1.26
4.8
Hysteresis of Schmitt trigger inputs
Vhys
-
-
LOW level output voltage at 3mA sink current
VOL
0
0.4
Pulse width of spikes which must be suppressed by
the input filter
tSP
0
50
Input current each I/O pin with an input voltage
between 0.1V and 0.9VIN_max
Ii
-10
10
SCL clock frequency
fSCL
-
100
Hold time (repeated) START condition. After this
period, the first clock pulse is generated
tHD;STA
4.0
-
LOW period of the SCL clock
tLOW
4.7
-
High period of the SCL clock
tHIGH
4.0
-
Set-up time for repeated START condition
tSU;STA
4.7
-
Data hold time
tHD;DAT
0
3.45
Data set-up time
tSU;DAT
250
-
Set-up time for STOP condition
tSU;STO
4.0
-
Bus free time between a STOP and START condition
tBUF
4.7
-
※6 _{STANDARD-MODE and FAST-MODE 2-wire serial interface devices must be able to transmit or receive at that speed.}
The maximum bit transfer rates of 100 kbit/s for STANDARD-MODE devices and 400 kbit/s for FAST-MODE devices
This transfer rates is provided the maximum transfer rates, for example it is able to drive 100 kbit/s of clocks with FAST-MODE.
FAST-MODE^※6
Min.
Max.
-0.5
0.5
1.26
4.8
0.15
-
0
0.4
0
50
-10
10
-
400
0.6
-
1.3
-
0.6
-
0.6
-
0
0.9
100
-
0.6
-
1.3
-
4/5
Unit
V
V
V
V
ns
uA
kHz
us
us
us
us
us
ns
us
us
Definition of timing on the 2-wire serial interface
tHIGH
SCL
SDA
tHD : STA
tBUF
tSU : DAT
tLOW
Fig.4 Definition of timing for serial data
tHD : DAT
SCL
SDA
tSU : STA
tHD : STA
tSU : STO
START BIT
STOP BIT
Fig.5 Definition of timing for START and STOP bit
REV. A