BU64240GWZ Datasheet, PDF (3/6 Pages) Rohm – Silicon Monolithic Integrated Circuit

Package Outline
3/5
Pin Arrangement (Top View)
Top View
1
A PS
2
SCL
3
SDA
B OUT GND VCC
Fig.2 BU64240GWZ Pin Arrangement (Top View)
Side View
Bottom View
Fig.1 UCSP30L1 Package (Unit: mm)
I2C BUS Format (Fast mode: SCL=400kHz )
Block Diagram
0.1～10uF
VCC
VCC
PS
Power Save
TSD & UVLO
VCC
BandGap
I2C bus
SDA
Interface
&
SCL
slew rate control
10
OSC 10bit DAC
BandGap
VREF
Pre Driver
V/I
convertor
ISINK
OUT
RNF
=0.5Ω
GND
Fig.3 BU64240GWZ Block Diagram
Write mode（R/W = 0)
Output from Master
Output from Slave
Update
S 0 0 0 1 1 0 0 R/W A PS EN W2 W1 W0 M D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A
Read mode
S 0 0 0 1 1 0 0 0 A PS EN W2 W1 W0 M ※ ※ A
W rite
Update W (register address)
S 0 0 0 1 1 0 0 1 A PS EN W2 W1 W0 M CD9 CD8 A CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 A
Read
S : start signal
A : acknowledge
P : stop signal
nA : non acknowledge
※ : Don`t care
Register
name
PS
EN
M
W2W1W0
D9～D0
Setting item
Serial power save
OUT pin status
Mode select signal
Register address
Limit Voltage
Operating parameter1
Operating parameter2
Operating parameter3
Operating parameter4
Description
'0' = Standby mode, '1' = Operating mode
'0' = Hi-impedance, '1' = Constant current sink.
'0' = ISRC Mode Disabled, '1' = ISRC Mode Enabled
‘000’ = Limit Voltage setting, '001' = Operating parameter setting1
‘010’ = Operating parameter setting2, ‘011’ = Operating parameter setting 3
‘100’ = Operating parameter setting4
Target position DAC code[D9:D0]
Resonance frequency setting[D7:D3], Slew rate speed setting[D1:D0]
VCM un-control current setting1[D9:D0]
VCM un-control current setting2[D9:D0]
Step resolution[D7:D5] ( Minimum step resolution = 1LSB@10bit_DAC)
Step time setting[D4:D0] ( Minimum step time resolution = 50us )
REV. A