BD9E302EFJ Datasheet, PDF (34/44 Pages) Rohm – Integrated MOSFET Single Synchronous Buck DC/DC Converter

BD9E302EFJ
Datasheet
 PCB Layout Design
In the buck DC/DC converter, a large pulsed current flows in two loops. The first loop is the one into which the current flows
when the High Side FET is turned on. The flow starts from the input capacitor CIN, runs through the FET, inductor L and
output capacitor COUT and back to ground of CIN via ground of COUT. The second loop is the one into which the current flows
when the Low Side FET is turned on. The flow starts from the Low Side FET, runs through the inductor L and output
capacitor COUT and back to ground of the Low Side FET via ground of COUT. Tracing these two loops as thick and short as
possible allows noise to be reduced for improved efficiency. It is recommended to connect the input and output capacitors,
in particular, to the ground plane. The PCB layout has a great influence on the DC/DC converter in terms of all of the heat
generation, noise and efficiency characteristics.
Figure 78. Current loop of buck converter
Accordingly, design the PCB layout with particular attention paid to the following points.
 Provide the input capacitor close to the IC VIN terminal as possible on the same plane as the IC.
 If there is any unused area on the PCB, provide a copper foil plane for the ground node to assist heat dissipation from
the IC and the surrounding components.
 Switching nodes such as SW are susceptible to noise due to AC coupling with other nodes. Trace to the coil as thick
and as short as possible.
 Provide lines connected to FB and COMP as far from the SW node.
 COMP terminal is sensitive to high frequency harmonic noise, it is recommended that the external components of this
terminal placed close to the pin.
 Provide the output capacitor away from the input capacitor in order to avoid the effect of harmonic noise from the
input.
SW1
OFF EN ON
-
+
J2
TP2
TP4
C5
TP3
C4
C1
BOOT
VIN
TP1
EN
AGND
ROHM
SEMICONDUCTOR
L1
SW
TP5
PGND
COMP
C6
R3
FB
R1
C8
TP6
EVK026
OFF EN ON
GND
VOUT
TP4
TP3
TP2
TP5
TP1
TP6
Top Layer
Bottom Layer
Figure 79. Example of sample board layout pattern
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27.Apr.2016 Rev.002