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BD95500MUV Datasheet, PDF (19/21 Pages) Rohm – Switching Regulator with MOSFET for DDR-SDRAM Cores
BD95500MUV
Technical Note
(11) Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example, the relation between each potential is as follows:
○When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
○When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes
operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
Pin A
N
N P+
Parasitic element
Resistor
Pin A
P
P+ N
P substrate
GND
Transistor (NPN)
Pin B
B
C
E
Pin B
Parasitic
element
N P+
N
P
P+ N
P substrate
Parasitic element GND
GND
Example of IC structure
B
C
E
Parasitic
GND element
Other adjacent elements
(12) Ground Wiring Pattern
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change
the GND wiring pattern of any external components, either.
●Power Dissipation
VQFN040V6060
5.0
④4.66W
4.5
4.0
③3.77W
3.5
3.0
2.5
2.0
1.5
1.0 ②1.00W
0.5 ①0.54W
0
0
25
50
75
100
125
150
Ambient Temperature :Ta [℃]
①IC unit time
θj-a=231.5℃/W
②1 layer (Substrate surface copper foil area : 0mm2)
θj-a=125.0℃/W
③4 layer (Substrate surface and bottom copper foil area : 20.2mm2
2nd and 3rd copper foil area : 5505mm2)
θj-a=33.2℃/W
④4 layer (all layers copper foil area : 5505mm2)
θj-a=26.8℃/W
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19/20
2010.05 - Rev.C