BD9745EKN Datasheet, PDF (18/22 Pages) Rohm – Silicon Monolithic Integrated Circuit

２.) Applying condition of VBAT voltage.
The up/down selector UDSEL1,2,4 is constructed by inverter circuit whose
power is VBAT, therefore it is possible that operation faults is happen to apply STB
voltage without applying VBAT voltage.
As a rule, VBAT voltage is applied before applying STB voltage, or applied at the
same time.
At the worst, when VBAT voltage is applied late from STB, VBAT voltage must be applied
within 50μsec from applying STB voltage.
STB
VBAT
　ｔ
Within 50μsec
　ｔ
Fig-8
18/21
３.) Recommended operating condition of using back-gate control.
The DC/DC converters of CH1,2,4 have back-gate control to cut the current pass of pmos parasitic diode. Using the back-gate control, it is limited by
the ability of pmos parasitic diode and pmos switching back-gate position.
When synchronous rectifying FET is OFF in normal operation and STB OFF, the inductor current flows to Hx through pmos parasitic diode (D2)
and pmos switching back-gate position (M2). As a result, the voltage of Lx increase to “output voltage + D2 forward voltage Vf + voltage drop of M2”.
When Hx voltage is set to 5V, this voltage exceed absolute maximum voltage of Lx by increasing input current to about 1.2A. So that it is possible to
break built-in FET.
Fig-10 shows recommended operating area of using back-gate control. When the relation between output voltage and input current is out of range,
it must be added schottky barrier diode between Lx and Hx. Using schottky barrier diode, back-gate control can be used not to exceed absolute
maximum voltage of Lx.
The DC/DC converter of CH1 must be added schottky barrier diode as it is explained in item 1).
Hx
D1 ON
()
M2
Normally L
M1
②
D2 _OFF
()
M3
Normally H
①
Lx
M4
① D2 Forward voltage　Vf
② M2 Drop due to On
resistance △V
Input Current
PGND
Fig - 9 Back gate control
2.0
1.5A @3.6V
1.5
1.2A @4.2V
1.0
0.8A @5.0V
Recommended region
0.5
0.0
0
1
2
3
4
5
6
Output voltage [V]
Fig - 10 Recommended operating area of using back-gate
４.) Setting the detection time for the short-circuit-protector (SCP).
The detection time for the SCP is user-adjustable by varying the capacitor connected at SCP (pin32).
The detection time [sec] = Cscp × Vtsc / Iscp
(Cscp : The capacitance、Vtsc : The Threshold voltage SCP、Iscp :The SCP output current)
Ex）Cscp = 0.1μF
The detection time = 0.1×10^-6 × 1 / {4×10^-6} = 25msec
As the built-in FET breaks by heat in shorting output, it is recommended that the SCP capacitor is used below 0.47μF.
REV. D