BU9832GUL-W_10 Datasheet, PDF (16/19 Pages) Rohm – WL-CSP EEPROM family SPI BUS

BU9832GUL-W
Technical Note
●Notes on power ON/OFF
○At power ON/OFF, set CS “H” (=Vcc).
When CS is “L”, this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may
cause malfunction, mistake write or so. To prevent these, at power ON, set CS “H”. (When CS is in “H” status, all
inputs are canceled.)
Vcc
Vcc
GND
Vcc
CS
GND
Good example Bad example
Fig.59 CS timing at power ON/OFF
(Good example) CS terminal is pulled up to Vcc.
At power OFF, take 10ms or higher before supply. If power is turned on without observing this condition,
the IC internal circuit may not be reset, which please note.
(Bad example) CS terminal is “L” at power ON/OFF.
In this case, CS always becomes “L” (active status), and EEPROM may have malfunction, mistake
write owing to noises and the likes.
Even when CS input is High-Z, the status becomes like this case, which please note.
○P.O.R. circuit
This IC has a P.O.R. (Power On Reset) circuit as mistake write countermeasure. After P.O.R. action, it gets in write disable
status. The P.O.R. circuit is valid only when power is ON, and does not work when power is OFF. When power is ON, if the
recommended conditions of the following tR, tOFF, and Vbot are not satisfied, it may become write enable status owing to
noises and the likes.
tR
Vcc
tOFF
Vbot
0
Fig.60 Rise waveform
Recommended conditions of t_R, t_OFF, Vbot
t_R
t_OFF
10ms or below
10ms or higher
100ms or below 10ms or higher
Vbot
0.3V or below
0.2V or below
●Noise countermeasures
○Vcc noise (bypass capacitor)
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a bypass capacitor (0.1µF) between IC Vcc and GND. At that moment, attach it as close to IC as
possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
○SCK noise
When the rise time (tR) of SCK is long, and a certain degree or more of noise exists, malfunction may occur owing to clock
bit displacement. To avoid this, a Schmitt trigger circuit is built in SCK input. The hysterisis width of this circuit is set about
0.2V, if noises exist at SCK input, set the noise amplitude 0.2Vp-p or below. And it is recommended to set the rise time (tR)
of SCK 100ns or below. In the case when the rise time is 100ns or higher, take sufficient noise countermeasures. Make the
clock rise, fall time as small as possible.
○ WP noise
During execution of write status register command, if there exist noises on WP pin, mistake in recognition may occur
and forcible cancellation may result, which please note. To avoid this, a Schmitt trigger circuit is built in WP input. In the
same manner, a Schmitt trigger circuit is built in SI input, SI input and HOLD input too.
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16/18
2010.10 - Rev.A