BU9832GUL-W_10 Datasheet, PDF (10/19 Pages) Rohm – WL-CSP EEPROM family SPI BUS

BU9832GUL-W
Technical Note
4. Status register write / read command
CS
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
00 0 0 0 0
bit 7
bit 6
bit 5 bi t4
bit 3
bit 2
bit 1
bit 0
0 1 ^WPEN ＊ ＊ ＊ BP1 BP0 ＊ ＊
SO ^High-Z
Fig.39 Status register write command
＊=Don't care
Write status register command can write status register data. The data can be written by this command are 2 bits^{* 1}, that is,
BP1 (bit3) and BP0 (bit2) among 8 bits of status register. By BP1 and BP0, write disable block of EEPROM can be set. As
for this command, set CS LOW, and input ope code of write status register, and input data. Then, by making CS HIGH,
EEPROM starts writing. Write time requires time of tE/W as same as write. As for CS rise, start CS after taking the last
data bit (bit0), and before the next SCK clock starts. At other timing, command is cancelled. Write disable block is
determined by BP1 and BP0, and the block can be selected from 1/4 of memory array, 1/2, and entire memory array.
(Refer to the write disable block setting table.) To the write disabled block, write cannot be made, and only read can be
made.
*1 3bits including 1WPEN (bit7)
CS
SCK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SI
0
0
0
0
01
0
1
SO
High-Z
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
WPEN 0 0 0 BP1 BP0 WEN R/B
Fig.40 Status register read command
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10/18
2010.10 - Rev.A