BU9796AFS-E2 Datasheet, PDF (15/32 Pages) Rohm – Standard LCD Segment Driver

BU9796Axxx Series MAX 80 segments (SEG20×COM4)
Datasheet
Co mm and
OSC IN_E N
(i nte rnal )
I CSE T
Internal OSC mode
External clock mode
INT oscillation
(in terna l)
EXT clock
(OSCIN )
Figure 15. Oscillator mode change timing
○Blink control (BLKCTL)
MSB
LSB
D7 D6 D5 D4 D3 D2 D1 D0
C
1
1
1
0
*
P1 P0
( * : Don’t care)
Set blink mode
Blink mode (Hz)
P1 P0 Reset initialize condition
OFF
0
0
○
0.5
0
1
1
1
0
2
1
1
The Blink cycle varies by fclk characteristic when the internal oscillation circuit is used.
Refer to the item of oscillation characteristic for the fclk characteristic.
○All Pixel control (APCTL)
MSB
LSB
D7 D6 D5 D4 D3 D2 D1 D0
C
1
1
1
1
1
P1 P0
All display set ON, OFF
APON
P1
Normal
0
All pixel ON
1
Reset initialize condition
○
APOFF
P0 Reset initialize condition
Normal
0
○
All pixel OFF
1
All pixels ON: All pixels are ON regardless of DDRAM data
All pixels OFF: All pixels are OFF regardless of DDRAM data
(Note) This command is valid in Display on status. The data of DDRAM don’t change by this command. If set both P1 and P0 =”1”, APOFF will be select.
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13.Jun.2014 Rev.003