BU7858KN_10 Datasheet, PDF (15/25 Pages) Rohm – Mixer & Selector ICs with 16bit D/A Converter

BU7858KN,BU7893GU
Technical Note
・Writing Protocol
The write protocol is shown below. The register address is transferred in a byte after the slave address and write
command are transferred. The third byte writes the data into the internal register that is indicated by the second byte.
After that, the register address is incremented on automatically (when the register address is between 00h and 16h).
However, when the register address reaches 16h, the register address does not change with the next byte transfer, rather,
it accesses the same register address (16h). The register address is incremented after transfer completion.
S 1 1 0 0 0 1 1 0 A A7 A6 A5 A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A
D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave address
Register address
Data
Data
R/W=0(Write)
Register address
Increment
Register address
Increment
from master to slave
from slave to master
A=Acknowledge
A=Non-Acknowledge
S=START condition
P=STOP condition
・Reading Protocol
It reads from the next byte after writing the slave address and R/W bit. The read register is the following address
accessed at the end. After that, the data of the address incremented is read out. The register addresses are
incremented after transfer completion.
S 1 1 0 0 0 1 1 1 A D7 D6 D5 D4 D3 D2 D1 D0 A
Slave address
Data
R/W=1(Read)
Register address
Increment
D7 D6 D5 D4 D3 D2 D1 D0 A P
Data
Register address
Increment
from master to slave
from slave to master
A=Acknowledge
A=Non-Acnkowledge
S=START condition
P=STOP condition
・Combined Reading Protocol
After specifying an internal address, it reads by generating resending start conditions and changing the direction of data
transfer. Afterwards, data from incremented addresses is read. The register addresses are incremented after transfer
completion. Compound writing is possible by writing R/W=0 after resending start condition.
S 1 1 0 0 0 1 1 0 A A7 A6 A5 A4 A3 A2 A1 A0 A Sr 1 1 0 0 0 1 1 1 A
Slave address
Register address
Slave address
R/W=0 ( Write)
R/W=1 ( Read)
D7 D6 D5 D4 D3 D2 D1 D0 A
Data
from master to slave
Register address
Increment
from slave to master
D7 D6 D5 D4 D3 D2 D1 D0 A P
Data
Register address
A=Acknowledge
Increment
A=Non-acknowledge
S=START condition
P=STOP condition
Sr=Repeated START condition
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15/24
2010.09 - Rev.A