BU7858KN_10 Datasheet, PDF (13/25 Pages) Rohm – Mixer & Selector ICs with 16bit D/A Converter

BU7858KN,BU7893GU
Technical Note
【BU7893GU】
・Timing Chart
SCLK
SIO
Tsc
Thc
AD[6] AD[5] AD[4]
AD[0] Direction DT[7]
DT[6]
DT[1]
DT[0]
SEL
Ts css
・Write Operation
SCLK
When direction is "1": Write operation
When direction is "0": Read operation
SIO
AD[6]
AD[5] AD[4]
AD[0]
DT[7]
DT[6]
Direction”H”
DT[1]
DT[0]
SEL
・Read Operation (mode 1): SO_ENABLE (bit0 at register address 14h)=0
SCLK
Tsd
SIO
AD[6]
AD[5]
AD[4]
AD[0]
Hi-Z DT[7]
Direction”L”
DT[6]
SEL
Output data
・Read Operation (mode 2): SO_ENABLE (bit0 at register address 14h)=1
SCLK
SIO
AD[6]
AD[5]
AD[4]
Tsd
AD[0]
Direction”L”
DT[1] DT[0]
SO
Hi-Z
DT[7]
DT[6]
DT[5]
DT[1]
DT[0] _Hi-Z
Output data
SEL
Fig.34 CPU I/F Timing Chart (BU7893GU)
DVDD_IO=1.62～3.3V, Ta=-30～+85℃
Parameter
Bit Length
SCLK Input Frequency
SCLK ‘L’ Pulse Width
SCLK ‘H’ Pulse Width
SCLK-SEL Set-up Time
Data Set-up Time
Data Hold Time
Symbol
Min
Ncha
16
FSCLK
-
Tlsclk
25
Thsclk
25
Tscss
10
Tsc
10
Thc
10
Delay Time of Data Output
Tsd
-
*It is recommended to use exclusive lines for CPU interface.
Limits
Typ
-
-
-
-
-
-
-
-
Max
-
15
-
-
-
-
-
30
Unit
Conditions
bit
MHz
ns
ns
ns
ns
ns
ns
MSB first
SIO: Time from SCLK falling edge
SO : Time from SCLK rising edge
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13/24
2010.09 - Rev.A