BD9130NV_14 Datasheet, PDF (15/25 Pages) Rohm – Synchronous Buck Converter with Integrated FET

BD9130NV
(5) Setting the Output Voltage
The output voltage VOUT is determined by the equation (6):
V_OUT  (R₂ / R₁ 1) V_ADJ ・・・(6)
Where:
VADJ is the Voltage at ADJ terminal (0.8V Typ)
The required output voltage may be determined by adjusting R1 and R2.
Adjustable output voltage range : 1.0V to 2.5V
6
SW
1
ADJ
L
Co
Output
R2
R1
Figure 34. Setting the Output Voltage
Use 1 kΩ to 100 kΩ resistor for R1. If a resistor with resistance higher than 100 kΩ is used, check the circuit and
calculate carefully for ripple voltage etc.
The lower limit of input voltage depends on the output voltage.
Basically, it is recommended to use the condition:
V_{CC Min}  V_OUT  1.3V
Figure 35. shows the necessary output current value at the
lower limit of input voltage. (DCR of inductor: 0.1Ω)
This data is the characteristic value, so it does not guarantee
the operation range.
3.9
3.7
3.5
3.3
Vo=2.5V
3.1
Vo=1.8V
Vo=2.0V
2.9
7. Cautions on PCB Layout
2.7
0
0.5
1
1.5
2
O^OUT^uP^tpU^uT^t C^CU^uR^rR^reENⁿT^t: :^IIOOO^UUU^TTT[[A[^AA]]
Figure 35. Minimum Input Voltage in each Output Voltage
R2
R1
RITH
③
CITH
1 _ADJ
2
VCC
3
ITH
4
GND
VCC
EN ⁸
EN
7
PVCC
6
L
SW
5
CIN
CO
PGND
②
①
VOUT
GND
Figure 36. Layout Diagram
① For the sections drawn with heavy line, use thick conductor pattern as short as possible.
② Layout the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor CO closer to
the pin PGND.
③ Layout CITH and RITH between the pins ITH and GND as near as possible with least necessary wiring.
Note: SON008V5060 (BD9130NV) has thermal FIN on the reverse of the package.
The package thermal performance may be enhanced by bonding the FIN to GND plane which occupies a large area
of PCB.
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TSZ22111・15・001
15/21
TSZ02201-0J3J0AJ00130-1-2
02.Oct.2014 Rev.002