BD9130NV_14 Datasheet, PDF (14/25 Pages) Rohm – Synchronous Buck Converter with Integrated FET

BD9130NV
(4) Calculating RITH, CITH for Phase Compensation
Since the Current Mode Control is designed to limit an inductor current, a pole (phase lag) appears in the low frequency
area due to a CR filter consisting of an output capacitor and a load resistance, while a zero (phase lead) appears in the
high frequency area due to the output capacitor and its ESR. Therefore, the phases are easily compensated by adding
a zero to the power amplifier output with C and R as described below to cancel a pole at the power amplifier.
A
Gain
[dB] ⁰
0
Phase
[deg]
-90
fp(Min)
fp(Max)
IOUTMin
IOUTMax
fZ(ESR)
fp 
1
2  R_O  C_O
f _{Z ESR}

2
1
 ESR C_O
Pole at power amplifier
When the output current decreases, the load resistance Ro
increases and the pole frequency decreases.
Figure 31. Open loop gain characteristics
1
fp_{Min}  _{2  ROMax  CO}
fp_{Max}

2

1
R_OMin
 C_O
Hz _{← with lighter load}
Hz ^{← with heavier load}
A
Gain
[dB]
0
0
Phase
[deg]
-90
fZ(Amp)
Zero at power amplifier
Increasing capacitance of the output capacitor lowers the
pole frequency while the zero frequency does not change.
(This is because when the capacitance is doubled, the
capacitor ESR is reduced to half.)
f_{Z Amp}

2

1
R_ITH
 C_ITH
Figure 32. Error amp phase compensation characteristics
VCC
CIN
L
EN ^VCC,PVCC SW
VOUT
VOUT
VOUT
ESR
RO
ITH
GND,PGND
CO
RITH
CITH
Figure 33. Typical Application
Stable feedback loop can be achieved by canceling the pole fp (Min) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
f _{Z Amp }  f _{PMin}
1
1


2  R_ITH  C_ITH 2  R_OMax  C_o
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TSZ02201-0J3J0AJ00130-1-2
02.Oct.2014 Rev.002