BD9489F Datasheet, PDF (14/39 Pages) Rohm – DCDC converter with current mode

BD9489F
Datasheet
As the startup, the retaining function of the output voltage operates as following to boost the output with less influence of PWM
duty.
1. IC operates the boost normally as PWM=High.
2. At the timing that PWM turns from High to Low, the OVP voltage is memorized into IC. VOVPkeep IC holds is above voltage
of the resolution. For instance, if OVP terminal voltage is 2.43V, the copied voltage into IC is 2.5V.
3. IC compares VOVPkeep and the OVP terminal voltage, if OVP is smaller than VOVPkeep, the boost pulse is output. That is,
the quick startup is realized by boosting to the higher voltage as one LSB than the present OVP during PWM=Low.
4. If OVP is larger than VOVPkeep, the boost pulse is stopped.
5. Even if the output voltage is discharged during PWM=Low, that is retained by the boost pulse which try to keep the OVP
voltage close to VOVPkeep, on the other hand.
○The low duty PWM operation of the retaining function of the output voltage
PWM
①
OVP
OVP COPY
②
④
③
GATE
Figure 20. The low duty PWM operation of the retaining function
In the method the boost pulse is output only as PWM=H, the output voltage is decreased as the low PWM or PWM=0%. On the
other hand, this product retains the output voltage VOUT by generating the boost pulse during PWM=L.
1. IC operates the boost normally as PWM=High.
2. At the timing that PWM turns from High to Low, the OVP voltage is memorized into IC. VOVPkeep IC holds is below voltage
of the resolution. For instance, if OVP terminal voltage is 2.43V, the copied voltage into IC is 2.4V.
3. The output voltage VOUT is discharged by the load such as the divided resister of the OVP terminal.
4. If OVP is smaller than VOVPkeep, the boost pulse is output. If OVP is larger than VOVPkeep, the boost pulse is stopped.
As PWM is 0%, the number 4 item state lasts continuously, the output voltage do not decrease by the discharge.
If the interval of PWM=H is smaller than four GATE clock after the soft start is completed, this sampling operation is stopped.
(On the other hand, the boost pulse is output during PWM=L.)
○The BIT rule of sampling OVP voltage
There are two cases sampling above voltage of the resolution and below voltage of that in the previous remark. The condition
which voltage will be sampled is described below.
The case sampling above voltage of LSB
・The state LED current is not enough (LED_OK=L)
・The state OVP is detecting
The case sampling below voltage of LSB
・The state LED current is enough (LED_OK=H)
・The state OVP is released
Once LED_OK=H is asserted, the logic LED_OK=H is latched till the reset.
Note: The reason sampling above voltage of LSB
The OVP detection stops DCDC at OVP=3V. If the below voltage of LSB is sampled as PWM turns to low, IC keeps 2.9V. This
tends to release OVP detection. This is why the above voltage is sampled in the OVP detection.
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TSZ22111・15・001
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TSZ02201-0F1F0C100250-1-2
29.Oct 2014 Rev.002