BD9489F Datasheet, PDF (10/39 Pages) Rohm – DCDC converter with current mode

BD9489F
Datasheet
○Pin 8: ADIM
This is the input pin for analog dimming signal. The ISENSE feedback point is set as 1/3 of this pin bias. If more than 3.0V
is input, ISENSE feedback voltage is clamped to limit to flow LED large current. In this condition, the input current is
caused. Please refer to <ISENSE> terminal explanation.
○Pin 9: RT
This is the DC/DC switching frequency setting pin. DCDC frequency is decided by
connected resistor.
○The relationship between the frequency and RT resistance value (ideal)
R _RT

15000
f_SW [kHz ]
[k]　
The oscillation setting ranges from 50kHz to 800kHz.
The setting example is separately described in the section ”3.2.5 DCDC
Oscillation Frequency Setting”
Figure 12. RT terminal circuit example
The fail logic indicating the abnormal state can be obtained by using the right
circuit example. The gate capacitor of M1 is limited to 200pF. RE1C001VN is
recommended as M1. The RT pin output the 2.0V(typ.) in the normal state and
drops to 0V in the latch off state. The fail voltage may be momentary unstable as
REG58 drops to 0V. But this can be prevented by connecting capacitor C1.
Please refer to section “2.7 Behavior List of the Protect Functions” or “3.5 Timing
Chart”.
○Pin 10: FB
This is the output terminal of error amplifier.
FB pin rises with the same slope as the SS pin during the soft-start period.
After soft -start completion (SS>3.7V), it operates as follows.
CH1:
STB
CH2:
REG58
CH3:
FAIL
When PWM=H, it detects ISENSE terminal voltage and outputs error signal compared to analog dimming signal (ADIM).
When PWM=L, IC holds the OVP voltage at the edge of PWM=H to L, and operates to hold the adjacent voltage. Please
refer to section “3.5 Timing Chart”.
It detects over boost (FBMAX) over FB=4.0V(typ). After the SS completion, if FB>4.0V and PWM=H continues 4clk GATE,
the CP charge is starts. After that, only the FB>4.0V is monitored, if CP charge continues to the CP=3.0V, IC will be
latched off. (Please refer to section “3.5.6 Timing Chart”.)
The loop compensation setting is described in section "3.4 Loop Compensation".
○Pin 11: ISENSE
This is the input terminal for the current detection. Error amplifier compares the
lower one among 1/3 of the voltage terminal ADIM analog dimming and
3.0V(typ). And it detects abnormal LED overcurrent at ISENSE=3.0V(typ) over.
If GATE terminal continues during four CLKs (equivalent to 40us at fosc =
100kHz), it becomes latch-off. (Please refer to section “3.5.7 Timing Chart”.)
1.0V
Gain=1/3
67mV
0 0.2
3.0 ADIM[V]
Figure 13. Relationship of the feedback voltage and ADIM
○Pin 12: GND
This is the GND pin of the IC.
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
10/36
Figure 14. ISENSE terminal circuit example
TSZ02201-0F1F0C100250-1-2
29.Oct 2014 Rev.002