BU9891GUL-W_12 Datasheet, PDF (13/26 Pages) Rohm – WLCSP EEPROM

BU9891GUL-W (4Kbit)
Datasheet
●Timing chart
1) Read cycle (READ)
～～
～～
～～
CS
*1
～～
SK
12
4
～～
～～
27 28
～～
DI
DO
High-Z
1 1 0 A7
～ ～ ^{A1 A0}
～～
*2
～～
～～
0 D15 D14
～ ～ ^{D1 D0 D15 D14}
～～
*1 Start bit
When data “1” is input for the first time after the rise of CS, this is recognized as a start bit. And when “1” is input after plural “0” are input, it is recognized
as a start bit, and the following operation is started. This is common to all the commands to described hereafter.
Figure 31. Read cycle
○When the read command is recognized, input address data (16bit) is output to serial. And at that moment, at taking A0,
in sync with the rise of SK, “0” (dummy bit) is output. And, the following data is output in sync with the rise of SK.
This IC has an address auto increment function valid only at read command. This is the function where after the above
read execution, by continuously inputting SK clock, the above address data is read sequentially. And, during the auto
increment, keep CS at “H”.
2) Write cycle (WRITE)
CS
SK
DI
DO
High-Z
12
4
1 0 1 A7
～～
～～
～～
～ ～ ^{A1 A0 D15 D14}
～～
tCS
～～
27
～～
～ ～ ^{D1 D0}
～～
STATUS
～～
～～
～～
tSV
BU～ ～SY ^READY
tE/W
Figure 32. Write cycle
○In this command, input 16bit data (D15 to D0) are written to designated addresses (Am to A0). The actual write starts
by the fall of CS of D0 taken SK clock.
When STATUS is not detected, (CS=”L” fixed) Max. 5ms in conformity with tE/W, and when STATUS is detected
(CS=”H”), all commands are not accepted for areas where “L” (BUSY) is output from D0, therefore, do not input any
command.
3) Write enable (WEN) / disable (WDS) cycle
～～
CS
SK
1
2
34
5
67
8 _{～ ～} 11
ENABLE=1 1
DISABLE=0 0 _{～ ～}
DI
1 00
～～
DO
High-Z
Figure 33. Write enable (WEN) / disable (WDS) cycle
○At power on, this IC is in write disable status by the internal RESET circuit. Before executing the write command, it is
necessary to execute the write enable command. And, once this command is executed, it is valid unitl the write disable
command is executed or the power is turned off. However, the read command is valid irrespective of write enable /
diable command. Input to SK after 6 clocks of this command is available by either “H” or “L”, but be sure to input it.
○When the write enable command is executed after power on, write enable status gets in. When the write disable
command is executed then, the IC gets in write disable status as same as at power on, and then the write command is
canceled thereafter in software manner. However, the read command is executable. In write enable status, even when
the write command is input by mistake, write is started. To prevent such a mistake, it is recommended to execute the
write disable command after completion of write.
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TSZ22111・15・001
13/22
TSZ02201-0R2R0G100440-1-2
3.SEP.2012 Rev.001