BD9329AEFJ-LB Datasheet, PDF (12/21 Pages) Rohm – 4.2V to 18V, 3A 1ch Synchronous Buck Converter integrated FET

BD9329AEFJ-LB
Datasheet
Layout Pattern Consideration
Two high pulsing current flowing loops exist in the buck regulator system. The first loop, when FET is ON, starts from the
input capacitors, to the VIN terminal, to the SW terminal, to the inductor, to the output capacitors, and then returns to the
input capacitor through GND. The second loop, when FET is OFF, starts from the low FET, to the inductor, to the output
capacitor, and then returns to the low FET through GND. To reduce the noise and improve the efficiency, please minimize
these two loop area. Especially input capacitor, output capacitor and low FET should be connected to GND plain.
PCB Layout may affect the thermal performance, noise and efficiency greatly. So please take extra care when designing
PCB Layout patterns.
VIN
CIN
FET
L
VOUT
COUT
Figure 26. Current loop in Buck regulator system
・The thermal Pad on the back side of IC has the great thermal conduction to the chip. So using the GND plain as broad and
wide as possible can help thermal dissipation. And a lot of thermal via for helping the spread of heat to the different layer
is also effective.
・The input capacitors should be connected as close as possible to the VIN terminal.
・When there is unused area on PCB, please arrange the copper foil plain of DC nodes, such as GND, VIN and VOUT for
helping heat dissipation of IC or circumference parts.
・To avoid the noise influence from AC combination with the other line, keep the switching line such as SW not extend as
much as possible, and trace shortly and thickly to coil.
・Keep sensitive signal traces such as trace connected FB and COMP away from SW pin.
・The inductor and the output capacitors should be placed close to SW pin as much as possible.
CIN
BST
VIN
EN
SW
GND
L
COUT
VOUT
Figure 27. The example of PCB layout pattern
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TSZ22111 • 15 • 001
12/18
TSZ02201-0323AAJ00320-1-2
27.Feb.2014 Rev.002