BD9329AEFJ-LB Datasheet, PDF (10/21 Pages) Rohm – 4.2V to 18V, 3A 1ch Synchronous Buck Converter integrated FET

BD9329AEFJ-LB
Datasheet
( i ) Choosing phase compensation resistor RCMP
The compensation resistor RCMP can be on following formula.
RCMP =
2πx VOUT x FCRS x COUT
[Ω]
VFB x GMP x GMA
Where
VOUT ; Output voltage, FCRS ; Cross over frequency, COUT ; Output Capacitor,
VFB ; internal feedback voltage (0.9V(TYP)), GMP ; Current Sense Gain (7.8A/V(TYP)) ,
GMA ; Error Amplifier Trans-conductance (300µA/V(TYP))
Setting VOUT= 3.3V, FCRS= 38kHz, COUT= 20µF;
RCMP =
2πx 3.3 x 38k x 20u
=
0.9 x 7.8 x 300u
7.48k ~= 7.5k
[Ω]
( ii ) Choosing phase compensation capacitor CCMP
For the stability of DC/DC converter, canceling the phase delay that derives from output capacitor COUT and
resistive load ROUT by inserting the phase advance.
The phase advance can be added by the zero on compensation resistor RCMP and capacitor CCMP.
Making Fz= FCRS / 6 gives a first-order estimate of CCMP.
Compensation Capacitor
CCMP=
1
[F]
2π x RCMP x Fz
Setting Fz= FCRS/6 = 6.3kHz;
Compensation Capacitor
CCMP=
1
= 3.54n ~= 3.3n [F]
2π x 7.5k x 6.3k
However, the best values of zero and FCRS are different between applications. After calculation above formula and
confirmation actual application, please decide values finally.
( iii ) The condition of the loop compensation stability
The stability of DC/DC converter is important. To secure the operating stability, please check the loop compensation
has the enough phase-margin. For the condition of loop compensation stability, the phase-delay must be less than
150 degree where Gain is 0 dB.
Feed forward capacitor CRUP boosts phase margin over a limited frequency range and is sometimes used to
improve loop response. CRUP will be more effective if RUP >> RUP||RDW
VOUT
RUP
RDW
CRUP
FB
－
＋
0.9V
COMP
RCMP
CCMP
Figure 21
A
Gain [dB]
0
PHASE 0
－90
－180
(a)
GBW(b)
F
FCRS
－90°
PHASE MARGIN
－180°
F
Figure 22
(3) Design of Feedback Resistance constant
Set the feedback resistance as shown below.
V_OUT
R1
R2
0.9V
＋
ERR
－
FB
VOUT =
R1 + R2
× 0.9
[V]
R2
Figure 23
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TSZ22111 • 15 • 001
10/18
TSZ02201-0323AAJ00320-1-2
27.Feb.2014 Rev.002