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BD9132MUV_12 Datasheet, PDF (11/20 Pages) Rohm – 2.7V to 5.5V, 3.0A 1ch Synchronous Buck Converter integrated FET | |||
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BD9132MUV
Datasheet
Switching Regulator Efficiency
Efficiency Å may be expressed by the equation shown below:
η= VOUTÃIOUT Ã100[%]= POUT Ã100[%]=
POUT
Ã100[%]
VinÃIin
Pin
POUT+PDα
Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows:
Dissipation factors:
1) ON resistance dissipation of inductor and FETï¼PD(I2R)
2) Gate charge/discharge dissipationï¼PD(Gate)
3) Switching dissipationï¼PD(SW)
4) ESR dissipation of capacitorï¼PD(ESR)
5) Operating current dissipation of ICï¼PD(IC)
1)PD(I2R)=IOUT2Ã(RCOIL+RON) (RCOIL[Ω]ï¼DC resistance of inductor, RON[Ω]ï¼ON resistance of FET, IOUT[A]ï¼Output
current.)
2)PD(Gate)=CgsÃfÃV (Cgs[F]ï¼Gate capacitance of FETãf[H]ï¼Switching frequencyãV[V]ï¼Gate driving voltage of FET)
3)PD(SW)=
Vin2ÃCRSSÃIOUTÃf
IDRIVE
(CRSS[F]ï¼Reverse transfer capacitance of FETãIDRIVE[A]ï¼Peak current of gate.)
4)PD(ESR)=IRMS2ÃESR (IRMS[A]ï¼Ripple current of capacitorãESR[Ω]ï¼Equivalent series resistance.)
5)PD(IC)=VinÃICC (ICC[A]ï¼Circuit current.)
Consideration on Permissible Dissipation and Heat Generation
As this IC functions with high efficiency without significant heat generation in most applications, no special
consideration is needed on permissible dissipation or heat generation. In case of extreme conditions,
however, including lower input voltage, higher output voltage, heavier load, and/or higher temperature, the
permissible dissipation and/or heat generation must be carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.
Because the conduction losses are considered to play the leading role among other dissipation mentioned above including
gate charge/discharge dissipation and switching dissipation.
4.0
â 3.56W
3.0
2.0
â 4 layers (Copper foil area : 5505mm2)
copper foil in each layers.
θj-a=35.1â/W
â¡ 4 layers (Copper foil area : 10.29m2)
copper foil in each layers.
θj-a=103.3â/W
⢠4 layers (Copper foil area : 10.29m2)
θj-a=178.6â/W
â£IC only.
θj-a=367.6â/W
â¡1.21W
1.0
â¢0.70W
â£0.34W
0
0 25 50
75 100105 125 150
Ambient temperature:Ta [â]
Fig.27 Thermal derating curve
(VQFN020V4040)
P=IOUT2ÃRON
RON=DÃRONP+(1-D)RONN
Dï¼ON duty (=VOUT/VCC)
RONHï¼ON resistance of Highside MOS FET
RONLï¼ON resistance of Lowside MOS FET
IOUTï¼Output current
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TSZ22111ï½¥15ï½¥001
11/18
TSZ02201-0J3J0AJ00140-1-2
02.MAR.2012 Rev.001
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