RV5C339A Datasheet, PDF (37/51 Pages) RICOH electronics devices division – 3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICs WITH VOLTAGE MONITORING FUNCTION

RV5C339A
4. Alarm and Periodic Interrupt
The RV5C339A incorporates the alarm circuit and the periodic interrupt circuit that are configured to generate
alarm signals and periodic interrupt signals, respectively, for output from the INTRA and INTRB pins as described
below.
1)Alarm Circuit
The alarm interrupt circuit is configured to generate alarm signals for output from the INTRA or INTRB, which is
driven low (enabled) upon the occurrence of a match between current time read by the time counters (the day-of-
week, hour, and minute counters) and alarm time preset by the alarm registers (the Alarm_W registers intended
for the day-of-week, hour, and minute digit settings and the Alarm_D registers intended for the hour and minute
digit settings). The Alarm_W outputs from INTRB pin, and the Alarm_D outputs from INTRA pin.
2)Periodic Interrupt Circuit
The periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals
in the level mode for output from the INTRA pin depending on the CT2, CT1, and CT0 bit settings in the control
register 1.
The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in the
control register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and CT0 bits in the
control register 1) as listed in the table below.
Flag bits
Enable bits
Output pin
Alarm signals
WAFG bit
(under control of Alarm_W registers) (D1 at Address Fh)
WALE bit
(D7 at Address Eh)
INTRB
Alarm signals
DAFG bit
(under control of Alarm_D registers) (D0 at Address Fh)
DALE bit
(D6 at Address Eh)
INTRA
Periodic interrupt signals
CTFG bit
CT2, CT1, and CT0 bits (D2 to D0 at Address Eh)
(D2 at Address Fh) (these bit settings of 0 disable the periodic interrupt circuit)
INTRA
· At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the control register 1, the INTRA and
INTRB pin are driven high (disabled).
· When two types of interrupt signals are output simultaneously from the INTRA pin, the output from the INTRA
pin becomes an OR waveform of their negative logic.
Example: Combined Output of Alarm Interrupt Signals from the INTRA pin Under Control of Alarm_D and periodic
interrupt Registers
Alarm_D
Priodic Interrupt
INTRA
In this event, which type of interrupt signal is output from the INTRA pin can be confirmed by reading
the DAFG and CTFG bit settings in the control register 2.
34