R1510S Datasheet, PDF (18/41 Pages) RICOH electronics devices division – Input Voltage Range (Maximum Rating) Max. 36.0V (50V)

R1510S
NO.EA-185-140724
Release Output Delay Time
The release output delay time (Power-on Reset Time (tDELAY)) of R1510SxxxC/D can be set by the capacitor of
CD pin. The relationship between the capacitor capacitance and tDELAY is as shown in the following equation.
tDELAY(s)=7.0×10⁵×CD(F)
The upper limit of the capacitance value for the CD pin capacitor is 1µF. The capacitor operates normally with
more than 1µF; however, if the setting time (tDELAY) is set longer, the setting time differences could become bigger.
Also, if the detect output delay time becomes longer; the response of the VD output pin will be slow to make a
momentary stop.
If the VDD pin voltage is decreased with more than the through rate as it is shown in the graph below, the IC
does not operate normally. If there’s any possibility of this, please minimize the voltage fluctuation of VDD pin by
using CIN.
Inp ¹⁰⁰
ut
Vol
tag
e
10
Fal
ling
Ti
me
1
TF
(μs
) _0.1
V_DD
Vpp
The detector cannot
maintain the
detection.
tf
0.01
0 1 2 3 4 5 6 7 8 9 10 11 12
Vpp (V)
V_DD Input Waveform
Thermal Shutdown
If the junction temperature (Tj) becomes more than 140°C(Typ.) due to the heat generation in the voltage
regulator, the output driver will be turned off to protect the IC and the voltage regulator output will be turned off. If
the junction temperature becomes less than 125°C(Typ.), the output driver will be turned on and the voltage
regulator output will be turned on. Unless the cause of the heat generation is not removed, the voltage regulator
repeats turns on and off, so the output voltage will be a pulsing form.
R1510SxxxD Voltage Setting
The voltage detector (VD) of R1510SxxxD detects the output voltage drop of the voltage regulator (VR). If the
VD release voltage is set to more than the VR output voltage, the VD will not be canceled even if the VR output
voltage returns to the normal value after VD detected the output voltage drop of VR. To avoid this, there have to
be voltage differences between the voltage regulator’s output voltage (VOUT) and the voltage detector’s release
voltage (+VDET). Also, the following conditions have to be met.
(VR Output Setting Voltage) x 0.964 > (VD Detect Setting Voltage) x1.03 x 1.075
In case of using the products with the VR output voltage and the VD detector threshold that is not met the above
conditions, please make sure to give greater consideration on the system operation before use.
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