DS5028E Datasheet, PDF (22/41 Pages) Richtek Technology Corporation – Integrated PMIC with 4-Channel Synchronous Buck Converters, 8 LDOs, and MTP Non-Volatile Memory for Industrial Applications

RT5028E
Layout Consideration
For the best performance of the RT5028E, the following
PCB layout guidelines must be strictly followed.
 Place the input and output capacitors as close as
possible to the input and output pins respectively for
good filtering.
 Keep the main power traces as wide and short as
possible.
 The switching node area connected to LX and inductor
should be minimized for lower EMI.
 Connect the GND and Exposed Pad to a strong ground
plane for maximum thermal dissipation and noise
protection.
 Directly connect the output capacitors to the feedback
network of each channel to avoid bouncing caused by
parasitic resistance and inductance from the PCB trace.
GND
Input/Output capacitors must be
placed as close as possible to the
Input/Output pins.
VOUTB1
GND
LX should be connected to Inductor by wide and short
trace, keep sensitive compontents away from this trace.
GND
56 55 54 53 52 51 50 49 48 47 46 45 44 43
VOUTL1 1
VIN VINL123 2
VOUTL2 3
VOUTL3 4
VOUTL6 5
VOUTL5 6
VIN VINL456 7
VOUTL4 8
VOUTL7 9
VIN VINL78 10
VOUTL8 1110
ENL4 12
ENL5 13
ENL6 14
GND
GND
GND
GND
GND
42 LXB2
41 LXB2
40 ENB2
39 VOUTB2S
38 VINB3 VIN
37 VINB3
36 LXB3
35 LXB3
34 AGND
GND
33 VOUTB3S
32 VINB4 VIN
31 LXB4
30 ENB3
29 VOUTB4S
15 16 17 18 19 20 21 22 23 24 25 26 27 28
VOUTB2
GND
VOUTB3
GND
VOUTB4
Connect the Exposed
Pad to a ground plane.
GND
Figure 2. PCB Layout Guide
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DS5028E-00 October 2016