DS8816A Datasheet, PDF (19/21 Pages) Richtek Technology Corporation – Dual-Phase PWM Controller with PWM-VID Reference

following equation :
I_RMS = I_OUT 
V_OUT
V_IN
 ^{}1
V_OUT
V_IN

The next step is to select proper capacitor for RMS current
rating. Use more than one capacitor with low Equivalent
Series Resistance (ESR) in parallel to form a capacitor
bank is a good design. Besides, placing ceramic capacitor
close to the Drain of the high-side MOSFET is helpful in
reducing the input voltage ripple at heavy load.
Output Capacitor Selection
The output filter capacitor must have ESR low enough
to meet output ripple and load transient requirement,
yet have high enough ESR to satisfy stability
requirements. Also, the capacitance must be high
enough to absorb the inductor energy going from a full
load to no load condition without tripping the OVP
circuit. Organic semiconductor capacitor(s) or special
polymer capacitor(s) are recommended.
MOSFET Selection
The majority of power loss in the step-down power
conversion is due to the loss in the power MOSFETs. For
low voltage high current applications, the duty cycle of
the high-side MOSFET is small. Therefore, the switching
loss of the high-side MOSFET is of concern. Power
MOSFETs with lower total gate charge are preferred in
such kind of application.
However, the small duty cycle means the low-side
MOSFET is on for most of the switching cycle. Therefore,
the conduction loss tends to dominate the total power
loss of the converter. To improve the overall efficiency, the
MOSFETs with low R_DS(ON) are preferred in the circuit
design. In some cases, more than one MOSFET are
connected in parallel to further decrease the on-state
resistance. However, this depends on the low-side
MOSFET driver capability and the budget.
Thermal Considerations
The junction temperature should never exceed the
absolute maximum junction temperature T_J(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
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DS8816A-00 September 2016
RT8816A
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
P_D(MAX) = (T_J(MAX) − T_A) / θ_JA
where T_J(MAX) is the maximum junction temperature, T_A is
the ambient temperature, and θ_JA is the junction-to-ambient
thermal resistance.
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θ_JA, is highly package dependent. For a
WQFN-20L 3x3 package, the thermal resistance, θ_JA, is
30°C/W on a standard JEDEC 51-7 high effective-thermal-
conductivity four-layer test board. The maximum power
dissipation at T_A = 25°C can be calculated as below :
P_D(MAX) = (125°C − 25°C) / (30°C/W) = 3.33W for a
WQFN-20L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for the fixed T_J(MAX) and the thermal
resistance, θ_JA. The derating curves in Figure 13 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
4.0
Four-Layer PCB
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 13. Derating Curve of Maximum Power
Dissipation
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