RF2722_1 Datasheet, PDF (19/26 Pages) RF Micro Devices – GSM/GPRS/EDGE RECEIVER

Proposed
RF2722
In TX mode the RF2722 can also switch to an alternate set of GPO settings defined by TRTXA at the rising edge of TX_EN pin
when TRTX_EN is programmed high. This functionality is used to redirect the T/R switch to RX mode during the synthesizer lock
time so that the PA output due to feed-through from the VCO will not violate the ETSI time-mask specification.
RX Mode
When RXEN rises, DC_TIME2 starts in the RF2722 and the part switches to the alternate GPO settings defined in TRDC. Once
the timer expires then the settings of the GPO's revert back to the originally programmed GPO SDI fields.
RXEN
DC_TIME2
GPO
TRDC
GPO1,2
TX Mode
When TXEN rises, the RF2722 GPOs switch to the alternate GPO settings defined in TRTXA. When TXEN falls, the RF2722 GPO
settings revert back to the originally programmed GPO SDI fields.
TX_EN
GPO
GPO1,2
TRTXA
GPO1,2
Device Control and Programming
The Polaris RF2722 VLIF/DCR IC provides a serial interface for programming the control settings. The interface consists of
eight registers that are accessed individually via a six-bit address word. (Two registers are unused at this time and are included
for future expansion.) The register map is shown below. Each register plus the six address bits requires an 18-bit transfer
(except register CF, which has 18 bits and so requires a 24-bit transfer). Additional 'padding' bits can be added between the
address bits and the data bits, if longer transfer lengths are needed. Since the RF2722 will be most likely used with the
RF6001/3 then it is expected that six such padding bits will be used in each transfer to bring the total number of bits up to 24.
This will then match the programming width of the RF6001/3.
Address
100000
100001
100010
100011
100100
100101
100110
100111
011111
Register
CRX1
CRX2
CRX3
CRX4
CRX5
CF
Reserved
Reserved
Reset
Description
AGC, standby modes, LO phase cal
DCOC and GPO
DCOC
DCOC
LNA, VCO, mixer current settings, Gain cal
Gain settings for the polyphase filters and LNA’s.
Reserved for future use.
Reserved for future use.
Writing this address resets all SDI bits to their default states.
Rev A4 DS050919
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