RX6501 Datasheet, PDF (6/10 Pages) RF Monolithics, Inc – 868.35 MHz Hybrid Receiver

Receiver Pulse Generator and RF Amplifier Bias
The receiver amplifier-sequence operation is controlled by the Pulse Gen-
erator & RF Amplifier Bias module, which in turn is controlled by the
PRATE and PWIDTH input pins, and the Power Down (sleep) Control Sig-
nal from the Bias Control function.
In the low data rate mode, the interval between the falling edge of one
RFA1 ON pulse to the rising edge of the next RFA1 ON pulse tPRI is set
by a resistor between the PRATE pin and ground. The interval can be ad-
justed between 0.1 and 5 µs. In the high data rate mode (selected at the
PWIDTH pin) the receiver RF amplifiers operate at a nominal 50%-50%
duty cycle. In this case, the start-to-start period tPRC for ON pulses to
RFA1 are controlled by the PRATE resistor over a range of 0.1 to 1.1 µs.
In the low data rate mode, the PWIDTH pin sets the width of the ON pulse
t_PW1 to RFA1 with a resistor to ground (the ON pulse width t_PW2 to RFA2
is set at 1.1 times the pulse width to RFA1 in the low data rate mode). The
ON pulse width t_PW1 can be adjusted between 0.55 and 1 µs. However,
when the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF
amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data
rate operation. In this case, the RF amplifiers are controlled by the PRATE
resistor as described above.
Both receiver RF amplifiers are turned off by the Power Down Control Sig-
nal, which is invoked in the sleep mode.
Receiver Mode Control
The receiver operating modes – receive and power-down (sleep), are con-
trolled by the Bias Control function, and are selected with the CNTRL1 and
CNTRL0 control pins. Setting CNTRL1 and CNTRL0 both high place the
unit in the receive mode. Setting CNTRL1 and CNTRL0 both low place the
unit in the power-down (sleep) mode. CNTRL1 and CNTRL0 are CMOS
compatible inputs. These inputs must be held at a logic level; they cannot
be left unconnected.
Receiver Event Timing
Receiver event timing is summarized in Table 1. Please refer to this table
for the following discussions.
Turn-On Timing
The maximum time t_PR required for the receive function to become opera-
tional at turn on is influenced by two factors. All receiver circuitry will be op-
erational 5 ms after the supply voltage reaches 2.2 Vdc. The BBOUT-
CMPIN coupling-capacitor is then DC stabilized in 3 time constants
(3*_tBBC). The total turn-on time to stable receiver operation for a 10 ms
power supply rise time is:
t_PR = 15 ms + 3*t_BBC
Sleep and Wake-Up Timing
The maximum transition time from the receive mode to the power-down
(sleep) mode t_RS is 10 µs after CNTRL1 and CNTRL0 are both low (1 µs
fall time).
The maximum transition time t_SR from the sleep mode to the receive mode
is 3*t_BBC, where t_BBC is the BBOUT-CMPIN coupling-capacitor time con-
stant. When the operating temperature is limited to 60 °C, the time required
to switch from sleep to receive is dramatically less for short sleep times, as
less charge leaks away from the BBOUT- CMPIN coupling capacitor.
Pulse Generator Timing
In the low data rate mode, the interval t_PRI between the falling edge of an
ON pulse to the first RF amplifier and the rising edge of the next ON pulse
to the first RF amplifier is set by a resistor R_PR between the PRATE pin and
ground. The interval can be adjusted between 0.1 and 5 µs with a resistor
in the range of 51 K to 2000 K. The value of the R_PR is given by:
R_PR = 404* t_PRI + 10.5, where t_PRI is in µs, and R_PR is in kilohms
In the high data rate mode (selected at the PWIDTH pin) the receiver RF
amplifiers operate at a nominal 50%-50% duty cycle. In this case, the peri-
od t_PRC from the start of an ON pulse to the first RF amplifier to the start of
the next ON pulse to the first RF amplifier is controlled by the PRATE re-
sistor over a range of 0.1 to 1.1 µs using a resistor of 11 K to 220 K. In this
case R_PR is given by:
R_PR = 198* t_PRC - 8.51, where t_PRC is in µs and R_PR is in kilohms
In the low data rate mode, the PWIDTH pin sets the width of the ON pulse
to the first RF amplifier t_PW1 with a resistor R_PW to ground (the ON pulse
width to the second RF amplifier t_PW2 is set at 1.1 times the pulse width to
the first RF amplifier in the low data rate mode). The ON pulse width t_PW1
can be adjusted between 0.55 and 1 µs with a resistor value in the range
of 200 K to 390 K. The value of R_PW is given by:
R_PW = 404* t_PW1 - 18.6, where t_PW1 is in µs and R_PW is in kilohms
However, when the PWIDTH pin is connected to Vcc through a 1 M resis-
tor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating
high data rate operation. In this case, the RF amplifiers are controlled by
the PRATE resistor as described above.
LPF Group Delay
The low-pass filter group delay is a function of the filter 3 dB bandwidth,
which is set by a resistor R_LPF to ground at the LPFADJ pin. The minimum
3 dB bandwidth f_LPF = 1445/R_LPF, where f_LPF is in kHz, and R_LPF is in kilo-
hms.
The maximum group delay t_FGD = 1750/f_LPF = 1.21*R_LPF, where t_FGD is in
µs, f_LPF in kHz, and R_LPF in kilohms.
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