RX6501 Datasheet, PDF (5/10 Pages) RF Monolithics, Inc – 868.35 MHz Hybrid Receiver

Antenna
RFIO
20
ESD
Choke
SAW
CR Filter
RX6501 ASH Receiver Block Diagram
RFA1
CN TRL1
CN TRL0
17
18
Bias Control
3
RFA1
SAW
Delay Line
Power
Down
Control
Log
VCC1: Pin 2
VCC2: Pin 16
GND1: Pin 1
GND2: Pin 10
GND3: Pin 19
NC: Pin 8
RREF: Pin 11
CMPIN: Pin 6
NC: Pin 4
NC: Pin 12
RFA2
Detector
Low-Pass
Filter
LPFADJ 9
R _LPF
Pulse Generator
& RF Amp Bias
PRATE 14
15 PWIDTH
R _PR
R _PW
BBOUT
BB
5
6
7
C _BBO
DS1
Ref
Thld
Threshold
Control
THLD1 13
11 RREF
R _TH1
R _REF
RXDATA
Figure 2
RX6500 Series ASH Receiver Block Diagram
Figure 2 is the general block diagram of the RX6500 series ASH receiver.
Please refer to Figure 2 for the following discussions.
Antenna Port
The only external RF components needed for the receiver are the antenna
and its matching components. Antennas presenting an impedance in the
range of 35 to 72 ohms resistive can be satisfactorily matched to the RFIO
pin with a series matching coil and a shunt matching/ESD protection coil.
Other antenna impedances can be matched using two or three compo-
nents. For some impedances, two inductors and a capacitor will be re-
quired. A DC path from RFIO to ground is required for ESD protection.
Receiver Chain
The output of the SAW filter drives amplifier RFA1. The output of RFA1
drives the SAW delay line, which has a nominal delay of 0.5 µs.
The second amplifier, RFA2, provides 51 dB of gain below saturation. The
output of RFA2 drives a full-wave detector with 19 dB of threshold gain. The
onset of saturation in each section of RFA2 is detected and summed to pro-
vide a logarithmic response. This is added to the output of the full-wave de-
tector to produce an overall detector response that is square law for low
signal levels, and transitions into a log response for high signal levels. This
combination provides excellent threshold sensitivity and more than 70 dB
of detector dynamic range. In combination with the 30 dB of AGC range in
RFA1, more than 100 dB of receiver dynamic range is achieved.
The detector output drives a gyrator filter. The filter provides a three-pole,
0.05 degree equiripple low-pass response with excellent group delay flat-
ness and minimal pulse ringing. The 3 dB bandwidth of the filter can be set
from 4.5 kHz to 1.8 MHz with an external resistor.
The filter is followed by a base-band amplifier which boosts the detected
signal to the BBOUT pin. When the receiver RF amplifiers are operating at
a 50%-50% duty cycle, the BBOUT signal changes about 10 mV/dB, with
a peak-to-peak signal level of up to 685 mV. For lower duty cycles, the mV/
dB slope and peak-to-peak signal level are proportionately less. The de-
tected signal is riding on a 1.1 Vdc level that varies somewhat with supply
voltage, temperature, etc. BBOUT is coupled to the CMPIN pin or to an ex-
ternal data recovery process (DSP, etc.) by a series capacitor. The correct
value of the series capacitor depends on data rate, data run length, and
other factors as discussed in the ASH Transceiver Designer’s Guide.
When the receiver is placed in the power-down (sleep) mode, the output
impedance of BBOUT becomes very high. This feature helps preserve the
charge on the coupling capacitor to minimize data slicer stabilization time
when the receiver switches out of the sleep mode.
Data Slicers
The CMPIN pin drives data slicer DS1, which convert the analog signal
from BBOUT back into a digital stream. Data slicer DS1 is a capacitively-
coupled comparator with provisions for an adjustable threshold. The
threshold, or squelch, offsets the comparator’s slicing level from 0 to 90
mV, and is set with a resistor between the RREF and THLD1 pins. This
threshold allows a trade-off between receiver sensitivity and output noise
density in the no-signal condition. For best sensitivity, the threshold is set
to 0. In this case, noise is output continuously when no signal is present.
This, in turn, requires the circuit being driven by the RXDATA pin to be able
to process noise (and signals) continuously.
This can be a problem if RXDATA is driving a circuit that must “sleep” when
data is not present to conserve power, or when it its necessary to minimize
false interrupts to a multitasking processor. In this case, noise can be great-
ly reduced by increasing the threshold level, but at the expense of sensitiv-
ity. The best 3 dB bandwidth for the low-pass filter is also affected by the
threshold level setting of DS1. The bandwidth must be increased as the
threshold is increased to minimize data pulse-width variations with signal
amplitude.
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©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
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RX6501-062905
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