R4S76410 Datasheet, PDF (99/1040 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
Addressing
Mode
Instruction
Format
Effective Address Calculation Method
Calculation Formula
Register
indirect with
displacement
@(disp:4, Rn)
Effective address is register Rn contents with Byte: Rn + disp
4-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte),
2 (word), or 4 (longword), according to the
Word: Rn + disp × 2
Longword: Rn + disp × 4
operand size.
Rn
disp
+
(zero-extended)
×
Rn
+ disp × 1/2/4
1/2/4
Indexed
@(R0, Rn)
register indirect
Effective address is sum of register Rn and Rn + R0
R0 contents.
Rn
+
Rn + R0
R0
GBR
indirect with
displacement
@(disp:8, GBR) Effective address is register GBR contents Byte: GBR + disp
with 8-bit displacement disp added.
Word: GBR + disp × 2
After disp is zero-extended, it is multiplied by
1 (byte), 2 (word), or 4 (longword), according ^{Longword: GBR + disp × 4}
to the operand size.
GBR
disp
+
(zero-extended)
×
GBR
+ disp × 1/2/4
1/2/4
Indexed GBR
indirect
@(R0, GBR)
Effective address is sum of register GBR and GBR + R0
R0 contents.
GBR
R0
+
GBR + R0
Rev. 2.00 Mar. 15, 2007 Page 49 of 986
REJ09B0346-0200