R4S76410 Datasheet, PDF (1030/1040 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Item
Page Revision (See Manual for Details)
Figure 25.35 Synchronous
950 Amended
DRAM Burst Write Bus Cycle
(Four Write Cycles)
CKIO
(Bank Active Mode: WRITE
Command, Same Row Address,
A25 to A0
WTRCD = 0 Cycle,
Tnop
Tc1
Tc2
Tc3
Tc4
tAD1
tAD1
tAD1
tAD1
Column
address
Column
address
Column
address
Column
address
tAD1
Figure 25.36 Synchronous
951
DRAM Burst Write Bus Cycle
(Four Write Cycles)
(Bank Active Mode: PRE + ACT +
WRITE Commands, Different Row
Addresses,
WTRCD = 0 Cycle, TRWL = 0
Cycle)
Amended
CKIO
A25 to A0
Tp
tAD1
Tpw
Tr
Tc1
Tc2
Tc3
Tc4
Row address
tAD1
tAD1
tAD1
tAD1
tAD1
Column
address
Column
address
Column
address
Column
address
Rev. 2.00 Mar. 15, 2007 Page 980 of 986
REJ09B0346-0200