R4S76410 Datasheet, PDF (326/1040 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Table 12.3 Address Space Map 2 (CMNCR.MAP = 1)
Physical Address
Area
Memory to be
Connected
Capacity
H'00000000 to
H'03FFFFFF
Area 0
Normal memory
Burst ROM
(Asynchronous)
64 Mbytes
Burst ROM
(Synchronous)
H'04000000 to
H'07FFFFFF
Area 1
Internal I/O register
area*³
64 Mbytes
H'08000000 to
H'0BFFFFFF
Area 2
Normal memory
64 Mbytes
Byte-selection SRAM
SDRAM
H'0C000000 to
H'0FFFFFFF
Area 3
Normal memory
64 Mbytes
Byte-selection SRAM
SDRAM
H'10000000 to
H'13FFFFFF
Area 4
Normal memory
64 Mbytes
Byte-selection SRAM
H'14000000 to
H'17FFFFFF
Area 5*²
Burst ROM
(Asynchronous)
Normal memory
Byte-selection SRAM
64 Mbytes
H'18000000 to
H'1BFFFFFF
Area 6*²
MPX-I/O
Normal memory
Byte-selection SRAM
64 Mbytes
H'1C000000 to
H'1FFFFFFF
Area 7
Burst MPX-I/O
Reserved*¹
64 Mbytes
Notes: 1. Do not access the reserved area. If the reserved area is accessed, the correct
operation cannot be guaranteed.
2. For area 5, the CS5BBCR and CS5BWCR registers and the CS5B signal are valid.
For area 6, the CS6BBCR and CS6BWCR registers and the CS6B signal are valid.
3. Access the address indicated in section 24, List of Registers, for the on-chip I/O register
in area 1. Do not access area 1 addresses which are not described in the register map.
Otherwise, the correct operation cannot be guaranteed.
Rev. 2.00 Mar. 15, 2007 Page 276 of 986
REJ09B0346-0200