H83802 Datasheet, PDF (98/555 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 2 CPU
BSET, BCLR, BNOT, BTST
15
87
0
Operand : Register direct (Rn)
op
IMM
rn
Bit No.
: Immediate (#xx:3)
15
87
op
rm
0 _Operand
: Register direct (Rn)
rn
Bit No.
: Register direct (Rm)
15
87
0
op
rn
0 0 0 0 Operand : Register indirect (@Rn)
op
IMM
0 0 0 0 Bit No.
: Immediate (#xx:3)
15
87
0
op
rn
0 0 0 0 Operand : Register indirect (@Rn)
op
rm
0 0 0 0 Bit No.
: Register direct (Rm)
15
87
0
op
abs
Operand : Absolute address (@aa:8)
op
IMM
0 0 0 0 Bit No.
: Immediate (#xx:3)
15
87
0
op
abs
Operand : Absolute address (@aa:8)
op
rm
0 0 0 0 Bit No.
: Register direct (Rm)
BAND, BOR, BXOR, BLD, BST
15
87
0
Operand : Register direct (Rn)
op
IMM
rn
Bit No.
: Immediate (#xx:3)
15
87
0
op
rn
0 0 0 0 Operand : Register indirect (@Rn)
op
IMM
0 0 0 0 Bit No.
: Immediate (#xx:3)
15
87
0
op
abs
Operand : Absolute address (@aa:8)
op
IMM
0 0 0 0 Bit No.
: Immediate (#xx:3)
15
op
15
op
op
15
op
op
Legend:
op: Operation field
rm, rn: Register field
abs: Absolute address
IMM: Immediate data
87
87
87
IMM
rn
IMM
BIAND, BIOR, BIXOR, BILD, BIST
0 _Operand
: Register direct (Rn)
rn
Bit No.
: Immediate (#xx:3)
0
0 0 0 0 Operand
0 0 0 0 ^{Bit No.}
: Register indirect (@Rn)
: Immediate (#xx:3)
0
abs
Operand
IMM
0 0 0 0 Bit No.
: Absolute address (@aa:8)
: Immediate (#xx:3)
Figure 2.8 Instruction Formats of Bit Manipulation Instructions
Rev. 6.00 Mar 15, 2005 page 48 of 502
REJ09B0024-0600