H83802 Datasheet, PDF (281/555 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 9 Timers
When TCF overflows, OVFH is set. OVFL is set if the setting conditions are satisfied when the
lower 8 bits overflow. If a TCFL write and overflow signal output occur simultaneously, the
overflow signal is not output.
8-Bit Timer Mode:
• TCFH, OCRFH
In toggle output, TMOFH pin output is toggled when a compare match occurs. If a TCRF write
by a MOV instruction and generation of the compare match signal occur simultaneously,
TOLH data is output to the TMOFH pin as a result of the TCRF write.
If an OCRFH write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. The compare match signal is output in
synchronization with the TCFH clock.
If a TCFH write and overflow signal output occur simultaneously, the overflow signal is not
output.
• TCFL, OCRFL
In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF write
by a MOV instruction and generation of the compare match signal occur simultaneously,
TOLL data is output to the TMOFL pin as a result of the TCRF write.
If an OCRFL write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. As the compare match signal is output in
synchronization with the TCFL clock, a compare match will not result in compare match
signal generation if the clock is stopped.
If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not
output.
Clear Timer FH, Timer FL Interrupt Request Flags (IRRTFH, IRRTFL), Timer Overflow
Flags H, L (OVFH, OVFL), and Compare Match Flags H, L (CMFH, CMFL): When φ_W/4 is
selected as the internal clock, “Interrupt source generation signal” will be operated with φ_W and
the signal will be outputted with φ_W width. And, “Overflow signal” and “Compare match signal”
are controlled with 2 cycles of φ_W signals. Those signals are outputted with 2 cycles width of φ_W
(figure 9.6)
In active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the
term of validity of “Interrupt source generation signal”, same interrupt request flag is set. (1 in
figure 9.6) And, the timer overflow flag and compare match flag cannot be cleared during the term
of validity of “Overflow signal” and “Compare match signal”.
Rev. 6.00 Mar 15, 2005 page 231 of 502
REJ09B0024-0600