M306H3MC-XXXFP Datasheet, PDF (96/325 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H3MC-XXXFP/FCFP
Timer Ai mode register (i=2 to 4)
(When using two-phase pulse signal processing)
b6 b5 b4 b3 b2 b1 b0
0 1 0 00 1
Symbol
TA2MR to TA4MR
Address
After reset
039816 to 039A16
0016
Bit name
Function
RW
TMOD0 _{Operation mode select bit} ^{b1 b0}
RW
TMOD1
0 1 : Event counter mode
RW
MR0
To use two-phase pulse signal processing, set this bit to “0”.
RW
MR1
To use two-phase pulse signal processing, set this bit to “0”.
RW
MR2
To use two-phase pulse signal processing, set this bit to “1”.
RW
MR3
To use two-phase pulse signal processing, set this bit to “0”.
RW
TCK0
TCK1
Count operation type
select bit
0 : Reload type
1 : Free-run type
RW
Two-phase pulse signal
processing operation
0 : Normal processing operation
RW
select bit (Note 1)(Note 2) ^{1 : Multiply-by-4 processing operation}
Note 1: TCK1 bit is valid for timer A3 mode register. No matter how this bit is set, timers A2 and A4 always operate in
normal processing mode and x4 processing mode, respectively.
Note 2: If two-phase pulse signal processing is desired, following register settings are required:
• Set the UDF register’s TAiP bit to “1” (two-phase pulse signal processing function enabled).
• Set the TRGSR register’s TAiGH and TAiGL bits to ‘002’ (TAiIN pin input).
• Set the port direction bits for TAiIN and TAiOUT to “0” (input mode).
Figure 2.10.9. TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase
pulse signal processing with timer A2, A3 or A4)
Rev.1.00 2004.03.23 page 96 of 320