M306H3MC-XXXFP Datasheet, PDF (158/325 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H3MC-XXXFP/FCFP
2.12 A-D Converter
The microcomputer contains one A-D converter circuit based on 8-bit successive approximation method
configured with a capacitive-coupling amplifier. The analog inputs share the pins with P100 to P107, P95
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and P96. Similarly, ADTRG input shares the pin with P97. Therefore, when using these inputs, make sure
the corresponding port direction bits are set to “0” (= input mode).
When not using the A-D converter, set the VCUT bit to “0” (= Vref unconnected), so that no current will
flow from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A-D conversion result is stored in the ADi register bits for ANi, AN0i pins (i = 0 to 7).
Table 2.12.1 shows the performance of the A-D converter. Figure 2.12.1 shows the block diagram of the
A-D converter, and Figures 2.12.2 and 2.12.3 show the A-D converter-related registers.
Table 2.12.1. Performance of A-D Converter
Item
Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC)
Operating clock φAD (Note 2) fAD/divide-by-2 of fAD/divide-by-3 of fAD/divide-by-4 of fAD/divide-by-6 of
fAD/divide-by-12 of fAD
Resolution
8-bit
Integral nonlinearity error When AVCC = VREF = 5V
• With 8-bit resolution: ±3LSB
- ANEX0 and ANEX1 input (including mode in which external operation
amp is connected) : ±4LSB
Operating modes
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
Analog input pins
8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1)
A-D conversion start condition • Software trigger
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
• External trigger (retriggerable)
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Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 φAD cycles
• With sample and hold function
8-bit resolution: 28 φAD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: The fAD frequency must be 10 MHz or less.
Without sample-and-hold function, limit the fAD frequency to 250kHZ or less.
With the sample and hold function, limit the fAD frequency to 1MHZ or less.
Rev.1.00 2004.03.23 page 158 of 320