M306H3MC-XXXFP Datasheet, PDF (114/325 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H3MC-XXXFP/FCFP
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
03B016
After reset
X00000002
Bit
symbol
Bit
name
Function
RW
U0IRS UART0 transmit
0 : Transmit buffer empty (Tl = 1)
interrupt cause select bit 1 : Transmission completed (TXEPT = 1)
RW
U1IRS UART1 transmit
0 : Transmit buffer empty (Tl = 1)
interrupt cause select bit 1 : Transmission completed (TXEPT = 1)
RW
U0RRM UART0 continuous
0 : Continuous receive mode disabled
receive mode enable bit 1 : Continuous receive mode enable
RW
U1RRM UART1 continuous
0 : Continuous receive mode disabled
receive mode enable bit 1 : Continuous receive mode enabled
RW
CLKMD0 UART1 CLK/CLKS
Effective when CLKMD1 = “1”
select bit 0
0 : Clock output from CLK1
RW
1 : Clock output from CLKS1
CLKMD1 UART1 CLK/CLKS
0 : CLK output is only CLK1
select bit 1 (Note)
1 : Transfer clock output from multiple pins function
RW
selected
RCSP Separate UART0
CTS/RTS bit
0 : CTS/RTS shared pin
1 : CTS/RTS separated (CTS0 supplied from the P64 pin)
RW
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
(b7)
Note: When using multiple transfer clock output pins, make sure the following conditions are met:
U1MR register’s CKDIR bit = “0” (internal clock)
UART2 special mode register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
After reset
U0SMR to U2SMR 036F16, 037316, 037716 X00000002
Bit
symbol
Bit
name
IICM I²C mode select bit
ABC Arbitration lost detecting
flag control bit
0 : Other than I²C mode
1 : I²C mode
0 : Update per bit
1 : Update per byte
Function
BBS Bus busy flag
0 : STOP condition detected
1 : START condition detected (busy)
(b3) ^{Reserved bit}
Set to “0”
RW
RW
RW
RW
(Note1)
RW
ABSCS ^{Bus collision detect}
0 : Rising edge of transfer clock
RW
sampling clock select bit 1 : Underflow signal of timer Aj (Note 2)
ACSE Auto clear function
0 : No auto clear function
select bit of transmit
1 : Auto clear at occurrence of bus collision
RW
enable bit
SSS
Transmit start condition ^{0 : Not synchronizedi to RxDi}
select bit
1 : Synchronized to RxDi (Note 3)
RW
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
(b7)
Note 1: The BBS bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.).
Note 2: Underflow signal of timer A3 in UART0, underflow signal of timer A4 in UART1, underflow signal of timer A0 in UART2.
Note 3: When a transfer begins, the SSS bit is set to “0” (Not synchronized .to RxDi)
Figure 2.11.6. UCON Register and U0SMR to U2SMR Registers
Rev.1.00 2004.03.23 page 114 of 320