R1QBA4436RBG_15 Datasheet, PDF (9/30 Pages) Renesas Technology Corp – 144-Mbit DDR™II+ SRAM 2-word Burst Architecture (2.5 Cycle Read latency)

R1QBA4436RBG,R1QBA4418RBG
Power-up and Initialization Sequence
Datasheet
V_DD must be stable before K, /K clocks are applied.
- Recommended voltage application sequence : V_SS → V_DD → V_DDQ & V_REF → V_IN. (0 V to V_DD, V_DDQ < 200 ms)
- Apply V_REF after V_DDQ or at the same time as V_DDQ.
- Then execute either one of the following sequences.
1. Single Clock Mode
- Drive /DOFF high (/DOFF can be tied high from the start).
- Then provide stable clocks (K, /K) for at least 20 us.
Status
V_DD
V_DDQ
V_REF
/DOFF
K, /K
Power Up &
Unstable Stage
NOP &
Set-up Stage
Normal
Operation
Fix High (=Vddq)
SET-UP Cycle
2. PLL Off Mode (/DOFF tied low)
- In the "NOP and setup stage", provide stable clocks (K, /K) for at least 20 us.
PLL Constraints
1. These chips use the PLL. The clock input should have low phase jitter which is specified as tKC var.
2. The lower end of the frequency at which the PLL can operate is 250 MHz.
(Please refer to AC Characteristics table for detail.)
3. When the operating frequency is changed or /DOFF level is changed, setup cycles are required again.
R10DS0143EJ0200 Rev.2.00
Aug 01, 2014
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