R1QBA4436RBG_15 Datasheet, PDF (19/30 Pages) Renesas Technology Corp – 144-Mbit DDR™II+ SRAM 2-word Burst Architecture (2.5 Cycle Read latency)

R1QBA4436RBG,R1QBA4418RBG
Datasheet
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This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold
times for all latching clock edges.
V_DD and V_DDQ slew rate must be less than 0.1 V DC per 50 ns for PLL lock retention. PLL lock time
begins once V_DD , V_DDQ and input clock are stable.
It is recommended that the device is kept inactive during these cycles.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
Transitions are measured ±100 mV from steady-state voltage.
These parameters are sampled.
t_AVKH, t_IVKH, t_KHAX, t_KHIX spec is determined by the actual frequency regardless of Part Number (Marking
Name).
The following is the spec for the actual frequency.
0.30 ns for ≤550MHz & >500MHz
0.33 ns for ≤500MHz & >450MHz
0.40 ns for ≤450MHz & ≥250MHz
t_DVKH, t_KHDX spec is determined by the actual frequency regardless of Part Number (Marking Name). The
following is the spec for the actual frequency.
0.20 ns for ≤550MHz & >500MHz
0.22 ns for ≤500MHz & >450MHz
0.25 ns for ≤450MHz & >400MHz
0.28 ns for ≤400MHz & ≥250MHz
Remarks:
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Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted.
Control input signals may not be operated with pulse widths less than t_KHKL (min).
V_DDQ is +1.5 V DC. V_REF is +0.75 V DC.
Control signals are /LD and R-/W.
Setup and hold times of /BWx signals must be the same as those of Data-in signals.
R10DS0143EJ0200 Rev.2.00
Aug 01, 2014
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