R1QBA4436RBG_15 Datasheet, PDF (6/30 Pages) Renesas Technology Corp – 144-Mbit DDR™II+ SRAM 2-word Burst Architecture (2.5 Cycle Read latency)

R1QBA4436RBG,R1QBA4418RBG
Pin Descriptions
Datasheet
Name I/O type
Descriptions
SA
Input Synchronous address inputs: These inputs are registered and must meet the setup
and hold times around the rising edge of K. These inputs are ignored when device is
deselected.
/LD
Input Synchronous load: This input is brought low when a bus cycle sequence is to be
defined. This definition includes address and READ/WRITE direction.
R-/W
Input
Synchronous read / write Input: When /LD is low, this input designates the access
type (READ when R-/W is high, WRITE when R-/W is low) for the loaded address. R-
/W must meet the setup and hold times around the rising edge of K.
/BWx
Input
Synchronous byte writes: When low, these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals are sampled on the same
edge as the corresponding data and must meet setup and hold times around the
rising edges of K and /K for each of the rising edge comprising the WRITE cycle. See
Byte Write Truth Table for signal to data relationship.
K, /K
/DOFF
Input
Input
Input clock: This input clock pair registers address and control inputs on the rising
edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is
ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and
hold times around the clock rising edges. These balls cannot remain V_REF level.
PLL disable: When low, this input causes the PLL to be bypassed for stable, low
frequency operation.
TMS
TDI
Input
IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left unconnected if the
JTAG function is not used in the circuit.
TCK
Input
IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to V_SS if the JTAG
function is not used in the circuit.
ZQ
Input Output impedance matching input: This input is used to tune the device outputs to
the system data bus impedance. DQ and CQ output impedance are set to 0.2 × RQ,
where RQ is a resistor from this ball to ground. This ball can be connected directly to
V_DDQ, which enables the minimum impedance mode. This ball cannot be connected
directly to V_SS or left unconnected.
Note
R10DS0143EJ0200 Rev.2.00
Aug 01, 2014
Page 6 of 29