R10DS0206EJ0100 Datasheet, PDF (9/12 Pages) Renesas Technology Corp – 4Mb Advanced LPSRAM

RMLV0408E Series
Write Cycle (3) (CS# CLOCK)
A_0~18
CS#
t_WC
Valid address
t_AW
t_AS
t_CW
t_WR
WE#
t_WP ^*22
OE#
V_IH
OE# = “H” level
I/O_0~7
t_DW
t_DH
Valid Data
Note
22. t_WP is the interval between write start and write end.
A write starts when both of CS# and WE# become active.
A write is performed during the overlap of a low CS# and a low WE#.
A write ends when any of CS# or WE# becomes inactive.
R10DS0206EJ0100 Rev.1.00
2014.2.27
Page 9 of 10