R10DS0206EJ0100 Datasheet, PDF (10/12 Pages) Renesas Technology Corp – 4Mb Advanced LPSRAM

RMLV0408E Series
Low V_CC Data Retention Characteristics
Parameter
Symbol Min. Typ. Max. Unit
Test conditions^*24
V_CC for data retention
V_DR
1.5
─
─
V
Vin ≥ 0V,
CS# ≥ V_CC-0.2V
─
0.4^*23
2
A ~+25°C
Data retention current
─
─
3
A ~+40°C
I_CCDR
V_CC=3.0V, Vin ≥ 0V,
CS# ≥ Vcc-0.2V
─
─
5
A ~+70°C
─
─
7
A ~+85°C
Chip deselect time to data retention
t_CDR
Operation recovery time
t_R
0
5
─
─
─
─
ns
ms
See retention waveform.
Note 23. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
24. CS# controls address buffer, WE# buffer, OE# buffer, and I/O buffer. If CS# controls data retention mode, Vin
levels (address, WE#, OE#, I/O) can be in the high-impedance state.
Low Vcc Data Retention Timing Waveforms (CS# controlled)
CS# Controlled
V_CC
2.2V
t_CDR
CS#
2.7V 2.7V
t_R
V_DR
CS# ≥ V_CC - 0.2V
2.2V
R10DS0206EJ0100 Rev.1.00
2014.2.27
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