HD74LV125A Datasheet, PDF (9/10 Pages) Hitachi Semiconductor – Quad. Bus Buffer Gates with 3-state Outputs

HD74LV125A
5.00
5.30 Max
14
8
1
*0.20 ± 0.05
7
0.65
0.13 M
0.83 Max
0.10
As of January, 2003
Unit: mm
1.0
6.40 ± 0.20
0˚ – 8˚ _{0.50 ± 0.10}
*Ni/Pd/Au plating
Package Code
JEDEC
JEITA
Mass (reference value)
TTP-14DV
—
—
0.05 g
Rev.3.00 Jun. 03, 2004 page 9 of 9