HD74LV125A Datasheet, PDF (7/10 Pages) Hitachi Semiconductor – Quad. Bus Buffer Gates with 3-state Outputs

HD74LV125A
• Waveform − 1
Input A
tr
10 %
90 %
50 %V_CC
t_PLH
tf
90 %
50 %V_CC
10 %
t_PHL
Output Y
50 %V_CC
50 %V_CC
V_CC
GND
V_OH
V_OL
• Waveform − 2
tf
90 %
Input OE _{50 %VCC}
10 %
t_ZL
Waveform − A
Waveform − B
50 %V_CC
t_ZH
50 %V_CC
tr
10 %
90 %
50 %V_CC
t_LZ
V_OL + 0.3 V
t_HZ
V_OH − 0.3 V
V_CC
GND
V_CC
V_OL
V_OH
GND
Notes: 1. t_r ≤ 3 ns, t_f ≤ 3 ns
2. Input waveform: PRR ≤ 1 MHz, duty cycle 50%
3. Waveform−A is for an output with internal conditions such that the output is low except when
disabled by the output control.
4. Waveform−B is for an output with internal conditions such that the output is high except when
disabled by the output control.
Rev.3.00 Jun. 03, 2004 page 7 of 9