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R8C11 Datasheet, PDF (82/227 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES
R8C/11 Group
12.1 Timer (Timer X)
12.1 Timer X
The Timer X is an 8-bit timer with an 8-bit prescaler. Figure 12.1 shows the block diagram of Timer X.
Figures 12.2 and 12.3 show the Timer X-related registers.
The Timer X has five operation modes listed as follows:
• Timer mode:
The timer counts an internal count source.
• Pulse output mode:
The timer counts an internal count source and outputs the pulses
whose polarity is inverted at the timer the timer underflows.
• Event counter mode:
The timer counts external pulses.
• Pulse width measurement mode: The timer measures an external pulse's pulse width.
• Pulse period measurement mode:The timer measures an external pulse's period.
TXCK1 to TXCK0
=002
f1
f8 =012
f32 =102
f2 =112
INT1/CNTR0
Polarity
switching
TXMOD1 to TXMOD0
=002 or 012
=112
=102
TXS bit
Reload register
Counter
PREX register
TXMOD1 to TXMOD0 bits=012
CNTR0
TXOCNT bit
R0EDG =1
R0EDG=0
Q
Toggle flip-flop CK
Q
CLR
Figure 12.1 Timer X Block Diagram
Data bus
Reload register
Counter
TX register
Write to TX register
TXMOD1 to TXMOD0 bits=012
Timer X interrupt
INT1 interrupt
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TXMR
Address
008B16
After reset
0016
Bit symbol
Bit name
Function
RW
TXMOD0
Operation mode
select bit 0, 1
b1 b0
0 0 : Timer mode or
pulse period measurement mode
RW
TXMOD1
0 1 : Pulse output mode
1 0 : Event counter mode
RW
1 1 : Pulse width measurement mode
R0EDG
INT1/CNTR0
polarity switching Function varies with each operation mode
RW
bit(1)
TXS
Timer X count
0 : Stops counting
start flag
1 : Starts counting
RW
TXOCNT P30/CNTR0
select bit
Function varies depending on operation mode RW
TXMOD2 Operation mode
select bit 2
0 : Except in pulse period measurement mode
1 : Pulse period measurement mode
RW
TXEDG
Active edge
reception flag
Function varies depending on operation mode. RW
TXUND
Timer X under
flow flag
Function varies depending on operation mode. RW
NOTES:
1. The IR bit in the INT1IC register may be set to “1” (interrupt requested) when the R0EDG bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Factor” in the Usage Notes Reference Book.
Figure 12.2 TXMR Register
Rev.1.20 Jan 27, 2006 page 71 of 204
REJ09B0062-0120