R8C11 Datasheet, PDF (182/227 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES

R8C/11 Group
17.4 CPU Rewrite Mode
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Symbol
FMR1
Address
01B516
After reset
0100XX0X2
Bit symbol
Bit name
Function
RW
(b0)
Reserved bit
When read, its content is
RO
indeterminate.
FMR11 EW1 mode select bit⁽¹⁾
0: EW0 mode
1: EW1 mode
RW
(b3-b2) ^{Reserved bit}
When read, its content is
indeterminate.
RO
(b5-b4) ^{Reserved bit}
Set to “0”
RW
Nothing is assigned.
(b6)
When write, set to “0”.
(b7)
Reserved bit
Set to “0”
RW
NOTES:
1. To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no
interrupts will occur before writing “1” after writing “0”.
The FMR01 and FMR11 bits both are set to “0” by setting the FMR01 bit to “0”.
Flash memory control register 4
b7 b6 b5 b4 b3 b2 b1 b0
0
0000
Symbol
FMR4
Address
01B316
After reset
010000002
Bit symbol
Bit name
Function
RW
FMR40 ^{Erase-suspend function}
0: Invalid
RW
enable bit⁽¹⁾
1: Valid
FMR41
Erase-suspend request bit⁽²⁾ 0: Erase restart
1: Erase-suspend request
RW
(b5-b2) ^{Reserved bit}
Set to “0”
RO
FMR46 ^{Read status flag}
0: Disable reading
1: Enable reading
RO
(b7)
Reserved bit
Set to “0”
RW
NOTES:
1. To set this bit to “1”, write “0” and then “1” in succession. Make sure no interrupts will occur before
writing “1” after writing “0”.
2. This bit is valid only when the FMR40 bit is set to “1” (valid) and can only be written before ending an
erase after issuing an erase command. Other than this period, this bit is set to “0”.
In EW0 mode, this bit can be set to “0” and “1” by program.
In EW1 mode, this bit is automatically set to “1” if a maskable interrupt occurs during an erase operation
while the FMR40 bit is set to “1”. This bit can not be set to “1” by program. (Can be set to “0”.)
Figure 17.4 FMR1 Register and FMR4 Register
Rev.1.20 Jan 27, 2006 page 171 of 204
REJ09B0062-0120