S3A3 Datasheet, PDF (80/139 Pages) Renesas Technology Corp – Microcontroller

S3A3
Table 2.38 SCI timing (2) (2 of 2)
Parameter
Simple Slave access time
SPI
Slave output release time
2. Electrical Characteristics
Symbol
Min
t_SA
-
t_REL
-
Max
10 (PCLKA >
32 MHz),
6 (PCLKA ≤
32 MHz)
10 (PCLKA >
32 MHz),
6 (PCLKA ≤
32 MHz)
Unit
t_Pcyc
t_Pcyc
Test conditions
Figure 2.58 and
Figure 2.59
SCKn
master select
output
V_OH
t_SPCKWH
V_IH
SCKn
slave select input
(n = 0 to 4, 9)
t_SPCKWH
t_SPCKr
V_OH
V_OL
V_OL
t_SPCKWL
V_OH
t_SPcyc
t_SPCKf
V_OH
V_OL
t_SPCKr
V_IH
V_IL
V_IL
t_SPCKWL
V_IH
t_SPcyc
t_SPCKf
V_IH
V_IL
V_OH = 0.7 × VCC, V_OL = 0.3 × VCC, V_IH = 0.7 × VCC, V_IL = 0.3 × VCC
Figure 2.55 SCI simple SPI mode clock timing
SCKn
CKPOL = 0
output
SCKn
CKPOL = 1
output
SMISOn
input
SMOSIn
output
(n = 0 to 4, 9)
t_SU
t_H
MSB IN
t_Dr, t_Df
MSB OUT
DATA
t_OH
DATA
LSB IN
t_OD
LSB OUT
Figure 2.56 SCI simple SPI mode timing (master, CKPH = 1)
IDLE
MSB IN
MSB OUT
R01DS0307EU0100 Rev.1.00
Mar 7, 2017
Page 80 of 139