S3A3 Datasheet, PDF (111/139 Pages) Renesas Technology Corp – Microcontroller

S3A3
2.9 POR and LVD Characteristics
2. Electrical Characteristics
Table 2.62 Power-on reset circuit and voltage detection circuit characteristics (1)
Parameter
Voltage detection
level*¹
Power-on reset (POR)
Voltage detection circuit (LVD0)*²
Voltage detection circuit (LVD1)*³
Voltage detection circuit (LVD2)*⁴
Symbol
V_POR
V_{det0_0}
V_{det0_1}
V_{det0_2}
V_{det0_3}
V_{det0_4}
V_{det1_0}
V_{det1_1}
V_{det1_2}
V_{det1_3}
V_{det1_4}
V_{det1_5}
V_{det1_6}
V_{det1_7}
V_{det1_8}
V_{det1_9}
V_{det1_A}
V_{det1_B}
V_{det1_C}
V_{det1_D}
V_{det1_E}
V_{det1_F}
V_{det2_0}
V_{det2_1}
V_{det2_2}
V_{det2_3}
Min
1.27
3.68
2.68
2.38
1.78
1.60
4.13
3.98
3.86
3.68
2.98
2.89
2.79
2.68
2.58
2.48
2.38
2.10
1.84
1.74
1.63
1.60
4.11
3.97
3.83
3.64
Typ
1.42
3.85
2.85
2.53
1.90
1.69
4.29
4.16
4.03
3.86
3.10
3.00
2.90
2.79
2.68
2.58
2.48
2.20
1.96
1.86
1.75
1.65
4.31
4.17
4.03
3.84
Max
1.57
4.00
2.96
2.64
2.02
1.82
4.45
4.30
4.18
4.00
3.22
3.11
3.01
2.90
2.78
2.68
2.58
2.30
2.05
1.95
1.84
1.73
4.48
4.34
4.20
4.01
Unit Test conditions
V
Figure 2.84,
Figure 2.85
V
Figure 2.86
At falling edge
VCC
V
Figure 2.87
At falling edge
VCC
V
Figure 2.88
At falling edge
VCC
Note 1.
Note 2.
Note 3.
Note 4.
These characteristics apply when noise is not superimposed on the power supply. When a setting causes this voltage detection
level to overlap with that of the voltage detection circuit, it cannot be specified whether LVD1 or LVD2 is used for voltage
detection.
# in the symbol Vdet0_# denotes the value of the OFS1.VDSEL1[2:0] bits.
# in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits.
# in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[2:0] bits.
R01DS0307EU0100 Rev.1.00
Mar 7, 2017
Page 111 of 139