7643 Datasheet, PDF (79/121 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7643 Group
Timing Requirements
In Vcc = 3 V
Table 18 Timing requirements (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Symbol
Parameter
tW(RESET)
Reset input “L” pulse width
tC(XIN)
Main clock input cycle time (Note)
tWH(XIN)
Main clock input “H” pulse width
tWL(XIN)
Main clock input “L” pulse width
tC(XCIN)
Sub-clock input cycle time
tWH(XCIN)
Sub-clock input “H” pulse width
tWL(XCIN)
Sub-clock input “L” pulse width
tC(INT)
INT0, INT1 input cycle time
tWH(INT)
INT0, INT1 input “H” pulse width
tWL(INT)
INT0, INT1 input “L” pulse width
td(φ -TOUT)
Timer TOUT delay time
tC(SCLKE)
Serial I/O external clock input cycle time
tWH(SCLKE)
Serial I/O external clock input “H” pulse width
tWL(SCLKE)
Serial I/O external clock input “L” pulse width
tsu(SRXD-SCLKE) Serial I/O input setup time (external clock)
th(SCLKE-SRXD) Serial I/O input hold time (external clock)
td(SCLKE-STXD) Serial I/O output delay time (external clock)
tv(SCLKE-SRDY) Serial I/O SRDY valid time (external clock)
tc(SCLKI)
Serial I/O internal clock output cycle time
tWH(SCLKI)
Serial I/O internal clock output “H” pulse width
tWL(SCLKI)
Serial I/O internal clock output “L” pulse width
tsu(SRXD-SCLKI) Serial I/O input setup time (internal clock)
th(SCLKI-SRXD) Serial I/O input hold time (internal clock)
td(SCLKI-STXD) Serial I/O output delay time (internal clock)
Limits
Unit
Min.
Typ. Max.
2
µs
41.66
ns
0.4•tc(XIN)
ns
0.4•tc(XIN)
ns
200
ns
0.4•tc(XCIN)
ns
0.4•tc(XCIN)
ns
250
ns
110
ns
110
ns
17
ns
450
ns
220
ns
190
ns
20
ns
15
ns
34
ns
35
ns
300
ns
0.5•tc(SCLKI) – 5
ns
0.5•tc(SCLKI) – 5
ns
20
ns
5
ns
5
ns
Note: Make sure not to exceed 6 MHz of φ, in other words, tc(φ) ≥ 166.66 ns).
Rev.2.00 Aug 28, 2006 page 79 of 119
REJ03B0054-0200