7643 Datasheet, PDF (40/121 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7643 Group
(2) Burst Transfer Mode
When the DMAC Channel x Transfer Mode Selection Bit (DxTMS)
is set to “1”, the respective DMAC channel operates in the burst
transfer mode.
In the burst transfer mode, the DMAC continually transfers the
number of bytes of data specified by the Transfer Count Register
for one transfer request. Other than this, the burst transfer mode
operation is the same as the cycle steal mode operation.
Priority
The DMAC places a higher priority on Channel-0 transfer requests
than on Channel-1 transfer requests.
If a Channel-0 transfer request occurs during a Channel-1 burst
transfer operation, the DMAC completes the next transfer source
and destination read/write operation first, and then starts the
Channel-0 transfer operation. As soon as the Channel-0 transfer is
completed, the DMAC resumes the Channel-1 transfer operation.
When an interrupt request occurs during any DMA operation, the
transfer operation is suspended and the interrupt process routine
is initiated. During the interrupt operation, the DMAC automatically
sets the corresponding DMAC Channel x (x = 0, 1) Suspend Flag
(DxSFI) to “1”. As soon as the CPU completes the interrupt opera-
tion, the DMAC clears the flag to “0” and resumes the original
operation from the point where it was suspended.
The suspended transfer due to the interrupt can also be resumed
during its interrupt process routine by writing “1” to the DMAC
Channel x (x = 0,1) Enable Bit (DxCEN).
The timing charts for a burst transfer caused by a hardware-re-
lated transfer request are shown in Figure 33.
φ
OUT
SYNCOUT
RD
WR
Address
Data
DMAOUT
(Port P33)
Transfer request
source (“L” active)
Transfer request source
sampling
Reset of transfer request
source sampling
LDA $zz
STA $zz
(First cycle)
DMA transfer
STA $zz
(Second cycle)
PC
PC + 1
ADL1, 00 PC + 2
DMA source DMA destina-
add. 1
tion add. 1
DMA source DMA destina-
add. 2
tion add. 2
PC + 3
A5
ADL1
Data
85
DMA
data 1
DMA
data 1
DMA
data 2
DMA
data 2
ADL2
Fig. 33 Timing chart for burst transfer caused by hardware-related transfer request
Rev.2.00 Aug 28, 2006 page 40 of 119
REJ03B0054-0200