H8S2169 Datasheet, PDF (784/1075 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 24 Power-Down State
Bit 4—Prescaler Select (PSS): Selects the WDT1 TCNT input clock. This bit also controls the
operation in a power-down mode transition. The operating mode to which a transition is made
after execution of a SLEEP instruction is determined in combination with other control bits. For
details, see the description of Clock Select 2 to 0 in section 14.2.2, Timer Control/Status Register
(TCSR).
Bit 4
PSS
Description
0
TCNT counts φ-based prescaler (PSM) divided clock pulses
When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode or software standby mode
(Initial value)
1
TCNT counts φ_SUB-based prescaler (PSS) divided clock pulses
When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode, watch mode^*, or subactive mode^*
When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode, watch mode, or high-speed mode
Note: * When a transition is made to watch mode or subactive mode, high-speed mode must
be set.
24.2.4 Module Stop Control Register (MSTPCR)
MSTPCRH
MSTPCRL
Bit
7654321076543210
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR comprises two 8-bit readable/writable registers that perform module stop mode control.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Rev. 3.00 Jan 18, 2006 page 756 of 1044
REJ09B0280-0300