H8S2169 Datasheet, PDF (610/1075 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 18A Host Interface X-Bus Interface (XBS)
18A.1.2 Block Diagram
Figure 18A.1 shows a block diagram of the HIF:XBS.
CS1
CS2/ECS2
CS3
CS4
IOR
IOW
HA0
Internal interrupt signals
IBF4 IBF3 IBF2 IBF1
Control logic
Host
interrupt
request
Fast
A20 gate
control
HIRQ1
HIRQ11
HIRQ12
HIRQ3
HIRQ4
GA20
HIFSD
Ports 4, 8, B
HDB7 to HDB0
IDR1
ODR1
STR1
IDR2
ODR2
STR2
HICR
IDR3
ODR3
STR3
IDR4
ODR4
STR4
HICR2
Internal data bus
Bus
interface
Legend:
IDR1: Input data register 1
IDR2: Input data register 2
ODR1: Output data register 1
ODR2: Output data register 2
STR1: Status register 1
STR2: Status register 2
HICR: Host interface control register 1
IDR3: Input data register 3
IDR4: Input data register 4
ODR3: Output data register 3
ODR4: Output data register 4
STR3: Status register 3
STR4: Status register 4
HICR2: Host interface control register 2
Figure 18A.1 Block Diagram of HIF:XBS
Rev. 3.00 Jan 18, 2006 page 582 of 1044
REJ09B0280-0300