H8S2169 Datasheet, PDF (635/1075 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 18B Host Interface LPC Interface (LPC)
18B.1.4 Register Configuration
Table 18B.2 lists the HIF:LPC registers.
Table 18B.2 Register Configuration
Name
System control register
System control register 2
Host interface control
register 0
Host interface control
register 1
Host interface control
register 2
Host interface control
register 3
LPC channel 3 address
register
Input data register 1
Abbrevia-
tion
SYSCR
SYSCR2
HICR0
R/W
Slave
R/W^*1
Host
—
R/W
—
R/W
—
HICR1
R/W
—
HICR2
R/W
—
HICR3
R
—
LADR3H R/W
—
LADR3L R/W
—
IDR1
R
W
Output data register 1
Status register 1
Input data register 2
ODR1
STR1
IDR2
R/W
R
R/(W)^*2 R
R
W
Output data register 2
Status register 2
Input data register 3
ODR2
STR2
IDR3
R/W
R
R/(W)^*2 R
R
W
Output data register 3
Status register 3
Two-way register 0MW
ODR3
STR3
R/W
R
R/(W)^*2 R
TWR0MW R
W
Two-way register 0SW
TWR0SW W
R
Initial
Value
H'09
H'00
H'00
H'00
H'00
—
H'00
H'00
—
—
H'00
—
—
H'00
—
—
H'00
—
—
Slave
Host
Address^*3 Address^*4
H'FFC4 —
H'FF83 —
H'FE40 —
H'FE41 —
H'FE42 —
H'FE43 —
H'FE34
H'FE35
H'FE38
H'FE39
H'FE3A
H'FE3C
H'FE3D
H'FE3E
H'FE30
H'FE31
H'FE32
H'FE20
H'FE20
—
—
H'0060 and
H'0064
H'0060
H'0064
H'0062 and
H'0066
H'0062
H'0066
LADR3^*5
+0 and +4
LADR3^*5 +0
LADR3^*5 +4
LADR3^*6
+16 /–16
LADR3^*6
+16 /–16
Rev. 3.00 Jan 18, 2006 page 607 of 1044
REJ09B0280-0300