HD64F2328VTE25 Datasheet, PDF (776/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
H'00000
EB0
H'01000
EB1
H'02000
EB2
H'03000
EB3
H'04000
EB4
H'05000
EB5
H'06000
EB6
H'07000
EB7
H'08000
This area is accessible as both a RAM
area and as a flash memory area.
H'FFBC00
H'FFDC00
H'FFEBFF
Flash memory
(user MAT)
EB8 to EB15
On-chip RAM
H'7FFFF
H'FFFBFF
Figure 17.77 Example of a RAM-Overlap Operation
Figure 17.77 shows an example of an overlap on block area EB0 of the flash memory.
Emulation is possible for a single area selected from among the eight areas, from EB0 to EB7, of
user MAT bank 0. The area is selected by the setting of the RAM2 to RAM0 bits in the RAMER
register.
(1) To overlap a part of the RAM on area EB0, to allow realtime programming of the data for this
area, set the RAMER register's RAMS bit to 1, and each of the RAM2 to RAM0 bits to 0.
(2) Realtime programming is carried out using the overlaid area of RAM.
In programming or erasing the user MAT, it is necessary to run a program that implements a series
of procedural steps, including the downloading of a on-chip program. In this process, set the
download area with FTDAR so that the overlaid RAM area and the area where the on-chip
program is to be downloaded do not overlap. An FTDAR setting of H'02 will cause part of the
tuned data area to overlap with part of the download area. When using the initial setting of
FTDAR, the data that is to be programmed must be saved beforehand in an area that is not used by
the system.
Rev.7.00 Feb. 14, 2007 page 742 of 1108
REJ09B0089-0700